1
Dan Patterson, Bindi Prasad, Gurbir Singh, Peter MacWilliams, Steve Hunt, Phil G Lee: Processor-cache protocol using simple commands to implement a range of cache configurations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 13, 2001: US06202125 (42 worldwide citation)

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A seco ...


2
Phil G Lee, Eileen Riggs: Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic. Intel Corporation, Owen L Lamb, January 4, 1994: US05276690 (36 worldwide citation)

An integrated circuit module in which an error detection circuit compares data generated internally on module with data generated externally from another substantially identical module. An error detect output is asserted upon the condition that data generated internally on module and data generated ...