1
Dan Patterson, Bindi Prasad, Gurbir Singh, Peter MacWilliams, Steve Hunt, Phil G Lee: Processor-cache protocol using simple commands to implement a range of cache configurations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 13, 2001: US06202125 (42 worldwide citation)

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A seco ...


2
Peter MacWilliams, Nitin V Sarangdhar, Matthew Fisch, Amit Merchant: Method and apparatus for snoop stretching using signals that convey snoop results. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 5, 1996: US05572703 (23 worldwide citation)

A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a b ...


3
Peter MacWilliams: Method and apparatus for evolving bus from five volt to three point three volt operation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 6, 1995: US05421734 (22 worldwide citation)

The present invention provides an apparatus for evolving a 5 volt V.sub.cc signaling environment to a 3.3 volt V.sub.cc signaling environment. A 5 volt bus connector and a 3.3 volt bus connector are provided with a key disposed at different locations on the respective connectors. A 5 volt circuit bo ...


4
Peter MacWilliams, James Akiyama, Kuljit S Bains, Douglas Gabel: Identifying and accessing individual memory devices in a memory channel. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 18, 2011: US07872892 (13 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more iden ...


5
Peter MacWilliams, James Akiyama, Kuljit S Bains, Douglas Gabel: Identifying and accessing individual memory devices in a memory channel. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 13, 2012: US08310854 (7 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more iden ...


6
Peter MacWilliams, Bindi Prasad, Manoji Khare, Dilip Sampath: Source synchronous interface between master and slave using a deskew latch. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 27, 2001: US06209072 (6 worldwide citation)

A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the sl ...


7
Peter MacWilliams, James Akiyama, Douglas Gabel: Micro-tile memory interfaces. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 4, 2011: US08032688 (4 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control ...


8
Peter MacWilliams, James Akiyama, Kuljit S Bains, Douglas Gabel: Identifying and accessing individual memory devices in a memory channel. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 22, 2011: US08064237 (4 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more iden ...


9
Peter MacWilliams, James Akiyama, Douglas Gabel: Memory controller interface for micro-tiled memory access. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 21, 2014: US08866830 (3 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control ...


10
Peter MacWilliams, James Akiyama, Douglas Gabel: Micro-tile memory interfaces. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 12, 2012: US08200883 (3 worldwide citation)

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control ...