1
Nicolas J Camilleri, Peter H Alfke, Christopher D Ebeling: FIFO memory system and method with improved determination of full and empty conditions and amount of data stored. Xilinx, Patrick T Bever, Lois D Cartier, August 13, 2002: US06434642 (77 worldwide citation)

A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current writ ...


2
Peter H Alfke, Alvin Y Ching, Scott O Frake, Jennifer Wong, Steven P Young: Clock-gating circuit for reducing power consumption. Xilinx, Julie Stephenson, Lois D Cartier, March 20, 2001: US06204695 (63 worldwide citation)

A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit ...


3
Raymond C Pang, Venu M Kondapalli, Jane W Sowards, Scott O Frake, Jennifer Wong, F Erich Goetting, Peter H Alfke, Schuyler E Shimanek: Programmable logic device with partial battery backup. Xilinx, Edel M Young, Scott R Brown, August 27, 2002: US06441641 (60 worldwide citation)

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the batt ...


4
Peter H Alfke: System for preventing radiation failures in programmable logic devices. Xilinx, Arthur J Behiel, Jeanette S Harms, August 15, 2000: US06104211 (58 worldwide citation)

A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit includes a state-comparison circuit that periodi ...


5
Charles R Erickson, Peter H Alfke: Input signal interface with independently controllable pull-up and pull-down circuitry. Xilinx, Edel M Young, Anthony C Murabito, October 19, 1999: US05969543 (54 worldwide citation)

An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circui ...


6
Robert O Conn, Peter H Alfke: User-controlled delay circuit for a programmable logic device. Xilinx, Arthur J Behiel Esq, Lois D Cartier, November 21, 2000: US06150863 (44 worldwide citation)

An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal ...


7
Charles R Erickson, Peter H Alfke: Input signal interface with independently controllable pull-up and pull-down circuitry. Xilinx, Edel M Young, Anthony C Murabito, February 4, 1997: US05600271 (38 worldwide citation)

An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circui ...


8
Peter H Alfke: FPGA control structure for self-reconfiguration. Xilinx, Adam H Tachner, Lois D Cartier, July 10, 2001: US06260139 (32 worldwide citation)

The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a re ...


9
Peter H Alfke: Programmable counter. Fairchild Camera and Instrument Corporation, Alan H MacPherson, Henry K Woodward, Robert C Colwell, April 11, 1978: US04084082 (30 worldwide citation)

A programmable counter is described having three cascaded counters, the first one of which is a dual modulus prescaler. The second counter is a resettable binary counter which is fed information from a programmable read-only memory as to the numbers of times the prescaler divisions are to be repeate ...


10
Peter H Alfke: Feedback apparatus for adjusting clock delay. Xilinx, E Eric Hoffman Esq, Edel M Young, December 14, 1999: US06002282 (28 worldwide citation)

A closed loop clock delay adjustment system measures the drift between the delay introduced by clock buffers and by delays inserted at the device data input pins. The system uses a reference delay at the input of a measurement flip-flop. The reference delay is defined to be an approximate average of ...