31
William S Wu, Peter D MacWilliams, Stephen Pawlowski, Muthurajan Jayakumar: Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 5, 1999: US05961621 (10 worldwide citation)

A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This vis ...


32
Peter D MacWilliams, William S Wu, Dilip K Sampath, Bindi A Prasad: Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 1, 2002: US06336159 (10 worldwide citation)

A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to ...


33
Gary A Solomon, Norman J Rasmussen, Peter D MacWilliams: Method and apparatus for executing multiple transactions within a single arbitration cycle. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 7, 1999: US05948094 (9 worldwide citation)

A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is ex ...


34
Stephen S Pawlowski, Peter D MacWilliams: Scalable, high bandwidth multicard memory system utilizing a single memory controller. Intel Corporation, Kenyon & Kenyon, November 30, 1999: US05996042 (9 worldwide citation)

A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem wi ...


35
Peter D MacWilliams, Dror Avni, Avi Liebermensch, Anan Baransy, Robert L Farrell: Parallel multistage synchronization method and apparatus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 30, 1996: US05488639 (8 worldwide citation)

A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first ...


36
Stephen Pawlowski, Peter D MacWilliams: Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 3, 1995: US05455957 (7 worldwide citation)

An apparatus and method for communicating characteristics about a memory module to a processor unit. A method and apparatus for communicating memory module characteristics, such as whether the module can communicate in a deterministic mode, memory size, memory speed, memory type and whether the memo ...


37
Peter D MacWilliams, Duane G Quiet: Independent timing compensation of write data path and read data path on a common data bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 3, 2000: US06128748 (7 worldwide citation)

An apparatus includes a read clock path to provide a read clock signal to a memory controller, wherein the read clock signal is to control timing of a memory controller when reading from a memory. The apparatus also includes a write clock path, independent of the read clock path, to provide a write ...


38
George Hayek, Brian Langendorf, Aniruddha Kundu, Gary Solomon, Peter D MacWilliams, James M Dodd: System resource arbitration mechanism for a host bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 27, 2002: US06442632 (7 worldwide citation)

A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune sys ...


39
Peter D MacWilliams, Nitin V Sarangdhar, Stephen S Pawlowski, Gurbir Singh: Data flow control mechanism for a bus supporting two-and three-agent transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 11, 2002: US06405271 (7 worldwide citation)

A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has re ...


40
Stephen S Pawlowski, Peter D MacWilliams, Nitin V Sarangdhar, Gurbir Singh: Method and apparatus for ordering writeback data transfers on a bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 13, 1999: US05923857 (6 worldwide citation)

A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to en ...