11
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Peter D MacWilliams, Stephen S Pawlowski, Michael W Rhodehamel: Method and apparatus for performing deferred transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 25, 1997: US05615343 (39 worldwide citation)

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents an ...


12
Gary A Solomon, Peter D MacWilliams, George R Hayek, Nicholas D Wade, Abid Asghar: Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 29, 1997: US05625779 (37 worldwide citation)

An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for ...


13
Frederick A Ware, Richard M Barth, Donald C Stark, Craig E Hampel, Ely K Tsern, Abhijit M Abhyankar, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: Apparatus and method for bus timing compensation. Rambus, Intel Corporation, Pennie & Edmonds, May 1, 2001: US06226757 (37 worldwide citation)

A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bu ...


14
Thomas J Holman, Peter D MacWilliams: Memory expansion channel for propagation of control and request packets. Intel Corporation, Seth Z Kalson, October 14, 2003: US06633947 (31 worldwide citation)

A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel f ...


15
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Scalable cache attributes for an input/output bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 22, 1997: US05651137 (30 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


16
Nitin V Sarangdhar, Gurbir Singh, Konrad Lai, Stephen S Pawlowski, Peter D MacWilliams, Michael W Rhodehamel: Highly pipelined bus architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 18, 1998: US05796977 (25 worldwide citation)

A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perfor ...


17
William S Wu, Stephen S Pawlowski, Peter D MacWilliams: Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 18, 1999: US05906001 (25 worldwide citation)

Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown ...


18
Stephen Pawlowski, Peter D MacWilliams: Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 30, 1996: US05513331 (23 worldwide citation)

An apparatus and method for assigning memory address information in a computer system. The present invention relates to computer systems having a plurality of ports or slots for coupling boards or other apparatus accessible to a processor of the computer system. The computer system further comprises ...


19
Stephen S Pawlowski, Peter D MacWilliams, David M Cowan, Howard S David: Asynchronous modular bus architecture with cache consistency. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 16, 1996: US05537640 (21 worldwide citation)

An asynchronous computer bus and method to maintain consistency of data contained in a cache and a memory which are each coupled to the bus. The bus comprises a cache hit indication means, a write access indication means, and a modified data indication means. A means is provided for invalidating a f ...


20
Peter D MacWilliams, Harry Muljono, Thomas J Mozdzen: Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 12, 2001: US06247136 (18 worldwide citation)

A method and apparatus for communicating signals between a source synchronous component and a non-source synchronous component of a system is described. The present invention provides a strobe signal from the source synchronous component that is delayed and used to latch data received from a non-sou ...