1
Michael W Leddige, Bryce D Horine, Randy Bonella, Peter D MacWilliams: Method and apparatus for implementing multiple memory buses on a memory module. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 1, 2003: US06587912 (302 worldwide citation)

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory ...


2
Michael W Leddige, Bryce D Horine, Randy Bonella, Peter D MacWilliams: Method for implementing multiple memory buses on a memory module. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 5, 2002: US06477614 (236 worldwide citation)

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory ...


3
Peter D MacWilliams, Robert L Farrell, Adalberto Golbert, Itzik Silas: Second level cache controller unit and system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 11, 1994: US05355467 (136 worldwide citation)

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus ...


4
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


5
Stephen S Pawlowski, Peter D MacWilliams, D Michael Bell: Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system. Intel Corporation, Kenyon & Kenyon, May 18, 1999: US05905876 (93 worldwide citation)

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlo ...


6
Peter D MacWilliams, Clair C Webb, Robert L Farrell: Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus. Intel Corporation, July 13, 1993: US05228134 (84 worldwide citation)

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cach ...


7
Peter D MacWilliams, Clair C Webb, Robert L Farrell: Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 8, 1994: US05293603 (65 worldwide citation)

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for opti ...


8
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparatus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 29, 2000: US06112016 (65 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


9
Sean T Murphy, Narjala Bhasker, Peter D MacWilliams, Stephen J Packer: Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 15, 1988: US04785396 (55 worldwide citation)

A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices cou ...


10
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparartus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1998: US05822767 (46 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...