1
Steven Frank, Henry Burkhardt III, Frederick D Weber, Linda Q Lee, John A Roskosz, Brett D Byers, Peter C Schnorr, David I Epstein: System for inserting instructions into processor instruction stream in order to perform interrupt processing. Sun Microsystems, October 13, 1998: US05822578 (62 worldwide citation)

Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. ...


2
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Christensen O Connor Johnson & Kindness, April 29, 1986: US04586130 (33 worldwide citation)

A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of ...


3
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Arnold White & Durkee, March 14, 1989: US04812971 (11 worldwide citation)

A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register ...


4
H Bruce Butts Jr, David N Cutler, Peter C Schnorr, Robert T Short: Central processing unit for a digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 9, 1990: US04893235 (9 worldwide citation)

A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register ...