1
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Micron Technology, Stephen A Gratton, January 11, 2005: US06841883 (389 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


2
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Semiconductor component having plate, stacked dice and conductive vias. Micron Technology, Stephen A Gratton, March 3, 2009: US07498675 (94 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


3
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Wafer level methods for fabricating multi-dice chip scale semiconductor components. Micron Technology, Stephen A Gratton, June 13, 2006: US07060526 (57 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


4
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts. Micron Technology, Stephen A Gratton, December 2, 2008: US07459393 (45 worldwide citation)

A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of the contact, ...


5
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components. Micron Technology, Stephen A Gratton, February 14, 2006: US06998717 (39 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


6
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Semiconductor component having plate and stacked dice. Micron Technology, Stephen A Gratton, May 29, 2007: US07224051 (21 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


7
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Stephen A Gratton, The Law Office Of Steve Gratton, December 23, 2004: US20040256734-A1

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


8
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Wafer level methods for fabricating multi-dice chip scale semiconductor components. Stephen A Gratton, The Law Office Of Steve Gratton, September 30, 2004: US20040188819-A1

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


9
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components. Stephen A Gratton, The Law Office Of Steve Gratton, March 3, 2005: US20050046038-A1

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


10
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts. Stephen A Gratton, The Law Office Of Steve Gratton, November 30, 2006: US20060270108-A1

A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of the contact, ...