1
Michael D Linderman, Jamison D Collins, Perry Wang, Hong Wang: Compiler and runtime for heterogeneous multiprocessor systems. Intel Corporation, Barnes and Thornburg, October 23, 2012: US08296743 (39 worldwide citation)

Presented are embodiments of methods and systems for library-based compilation and dispatch to automatically spread computations of a program across heterogeneous cores in a processing system. The source program contains a parallel-programming keyword, such as mapreduce, from a high-level, library-o ...


2
Natalie D Enright, Jamison D Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Sheaffer, Per Hammarlund: Mechanism to exploit synchronization overhead to improve multithreaded performance. Intel Corporation, David P McAbee, September 8, 2009: US07587584 (18 worldwide citation)

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchroniza ...


3
Hong Wang, Perry Wang, Ralph Kling, Neil A Chazin, John Shen: Quantization and compression for computation reuse. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, June 27, 2006: US07069545 (17 worldwide citation)

Software reuse instances are found from an execution trace through a process of quantization, discovery, and synthesis. Quantization includes mapping n-dimensional vectors that correspond to instructions, live-in states, and live-out states to one dimensional symbols, and arranging the symbols into ...


4
Perry Wang, Jamison Collins, Gautham Chinya, Hong Jiang, Hong Wang, Xinmin Tian, Guei Yuan Lueh: Programming environment for heterogeneous processor resource integration. Shireen Irani Bacon, May 10, 2011: US07941791 (15 worldwide citation)

Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruct ...


5
Xinmin Tian, Milind Girkar, David C Sehr, Richard Grove, Wei Li, Hong Wang, Chris Newburn, Perry Wang, John Shen: Thread-data affinity optimization using compiler. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 11, 2011: US08037465 (14 worldwide citation)

Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is t ...


6
Hong Wang, Tor Aamodt, Per Hammarlund, John Shen, Xinmin Tian, Milind Girkar, Perry Wang, Steve Shih wei Liao: Safe store for speculative helper threads. Intel Corporation, David P McAbee, February 2, 2010: US07657880 (13 worldwide citation)

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated with a Store instruction in a helper ...


7
Gerolf F Hoflehner, Shih wei Liao, Xinmin Tian, Hong Wang, Daniel M Lavery, Perry Wang, Dongkeun Kim, Milind Girkar, John P Shen: Methods and apparatuses for thread management of multi-threading. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 8, 2008: US07398521 (13 worldwide citation)

Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining re ...


8
Jamison Collins, Perry Wang, Bernard Lint, Koichi Yamada, Asit Mallick, Richard A Hankins, Gautham Chinya: Enabling multiple instruction stream/multiple data stream extensions on microprocessors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 3, 2010: US07768518 (12 worldwide citation)

Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of ...


9
Xinmin Tian, Shih wei Liao, Hong Wang, Milind Girkar, John Shen, Perry Wang, Grant Haab, Gerolf Hoflehner, Daniel Lavery, Hideki Saito, Sanjiv Shah, Dongkeun Kim: Methods and apparatus for reducing memory latency in a software application. Intel Corporation, Hanley Flight & Zimmerman, February 5, 2008: US07328433 (10 worldwide citation)

Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to pr ...


10
Hong Wang, Per Hammarlund, Xiang Zou, John Shen, Xinmin Tian, Milind Girkar, Perry Wang, Piyush Desai: Programmable event driven yield mechanism which may activate other threads. Intel Corporation, David P McAbee, February 3, 2009: US07487502 (8 worldwide citation)

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monito ...