1
Pedro Chaparro Monferrer, José González: Microarchitecture controller for thin-film thermoelectric cooling. Intel Corporation, Trop Pruner & Hu P C, January 4, 2011: US07865751 (19 worldwide citation)

A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to ...


2
Pedro Chaparro Monferrer, Grigorios Magklis, Jose Gonzalez, Antonio Gonzalez: Leakage power estimation. Intel Corporation, Caven & Aghevli, October 12, 2010: US07814339 (11 worldwide citation)

Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.


3
Qiong Cai, José González, Pedro Chaparro Monferrer, Grigorios Magklis, Antonio González: Thread migration to improve power efficiency in a parallel processing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 19, 2011: US07930574 (9 worldwide citation)

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing co ...


4
Christopher Wilkerson, Muhammad M Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez: Disabling cache portions during low voltage operations. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, January 24, 2012: US08103830 (6 worldwide citation)

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other ...


5
Christopher Wilkerson, Muhammad M Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez: Disabling cache portions during low voltage operations. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, October 16, 2012: US08291168 (5 worldwide citation)

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other ...


6
Pedro Chaparro Monferrer, José González: Microarchitecture controller for thin-film thermoelectric cooling. Intel Corporation, Trop Pruner & Hu P C, October 9, 2012: US08286016 (5 worldwide citation)

A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to ...


7
Qiong Cai, José González, Pedro Chaparro Monferrer, Grigorios Magklis, Antonio González: Thread migration to improve power efficiency in a parallel processing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 24, 2012: US08166323 (3 worldwide citation)

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing co ...


8
Pedro Chaparro Monferrer, Jose Gonzalez, Gregory Martin Chrysler: Microarchitecture control for thermoelectric cooling. Intel Corporation, Konrad Raynes & Victor, July 3, 2012: US08209989 (2 worldwide citation)

An integrated circuit is cooled by microarchitecture controlled Peltier effect cooling. In one embodiment, a temperature sensor thermally coupled to at least a portion of the integrated circuit of a die is adapted to provide an output as a function of the temperature of an integrated circuit portion ...


9
Pedro Chaparro Monferrer, Jaume Abella, Xavier Vera, Javier Carretero Casado: On-line testing for decode logic. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 29, 2011: US08069376 (2 worldwide citation)

Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In o ...


10
Christopher Wilkerson, Muhammad M Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez: Disabling cache portions during low voltage operations. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, June 13, 2017: US09678878

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other ...