1
Alexandre Acovic, Tak Hung Ning, Paul Michael Solomon: EEPROM having coplanar on-insulator FET and control gate. International Business Machines Corporation, Casey P August Esq, Whitham Curtis & Whitham, March 23, 1999: US05886376 (142 worldwide citation)

An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating l ...


2
Kevin Kok Chan, Christopher Peter D Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari: Method for making bonded metal back-plane substrates. International Business Machines Corporation, McGinn & Gibb P C, May 2, 2000: US06057212 (138 worldwide citation)

A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafer ...


3
Alexandre Acovic, Tak Hung Ning, Paul Michael Solomon: Method of making EEPROM having coplanar on-insulator FET and control gate. International Business Machines Corporation, Robert M Trepp, September 28, 1999: US05960265 (126 worldwide citation)

An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the ...


4
Paul Michael Solomon, Hon Sum Philip Wong: Method for making single and double gate field effect transistors with sidewall source-drain contacts. International Business Machines Corporation, June 30, 1998: US05773331 (95 worldwide citation)

The present invention concerns single-gate and double-gate field effect transistors having a sidewall source contact and a sidewall drain contact, and methods for making such field effect transistors. The channel of the present field effect transistors is raised with respect to the support structure ...


5
Cyril Cabral Jr, Kevin K Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Paul Michael Solomon, Ying Zhang: Self-aligned silicide process for silicon sidewall source and drain contacts. International Business Machines Corporation, Robert M Trapp Esq, McGinn & Gibb PLLC, November 11, 2003: US06645861 (57 worldwide citation)

A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal laye ...


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Cyril Cabral Jr, Kevin Kok Chan, Guy Moshe Cohen, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon: Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions. International Business Machines Corporation, Wan Yee Cheung Esq, McGinn & Gibb PLLC, January 17, 2006: US06987050 (12 worldwide citation)

A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first ...


8
Paul Michael Solomon: Switching circuit for large voltages. International Business Machines Corporation, Casey P August, Anne Vachon Dougherty, December 21, 1999: US06005415 (10 worldwide citation)

Method and apparatus for cascading devices wherein the output voltage is greater than the individual voltage capacity of the circuit components. The cascadable switch contains transistors connected so that the source and gate voltages on a given transistor are derived from the drain and source volta ...


9
Cyril Cabral Jr, Kevin Kok Chan, Guy Moshe Cohen, Kathryn Wilder Guarini, Christian Lavoie, Ronnen Andrew Roy, Paul Michael Solomon: Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby. International Business Machines Corporation, Wan Yee Cheung Esq, McGinn & Gibb PLLC, April 6, 2004: US06716708 (10 worldwide citation)

A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing ...


10
Kevin Kok Chan, Christopher Peter D&apos Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari: Back-plane for semiconductor device. International Business Machines Corporation, Casey P August, McGinn & Gibb PLLC, August 28, 2001: US06281551 (3 worldwide citation)

A back-plane for a semiconductor device, includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.