1
Samuel Hammond Duncan, Craig Durand Keefer, Thomas Adam McLaughlin, Paul Michael Guglielmi: Method and apparatus providing DMA transfers between devices coupled to different host bus bridges. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds P C, September 14, 1999: US05953538 (78 worldwide citation)

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units ...


2
Samuel Hammond Duncan, Glenn Arthur Herdeg, Ricky Charles Hetherington, Craig Durand Keefer, Maurice Bennet Steinman, Paul Michael Guglielmi: Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, March 5, 2002: US06353877 (34 worldwide citation)

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units ...


3
Samuel Hammond Duncan, Craig Durand Keefer, Thomas Adam McLaughlin, Paul Michael Guglielmi: Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds PC, January 4, 2000: US06012120 (22 worldwide citation)

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units ...


4
Samuel Hammond Duncan, Glenn Arthur Herdeg, Ricky Charles Hetherington, Craig Durand Keefer, Maurice Bennet Steinman, Paul Michael Guglielmi: Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, October 3, 2000: US06128711 (14 worldwide citation)

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units ...