1
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


2
Richard M Barth, Ely K Tsern, Craig E Hampel, Frederick A Ware, Todd W Bystrom, Bradley A May, Paul G Davis: Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain. Rambus, Blakely Sokoloff Taylor & Zafman, November 28, 2000: US06154821 (115 worldwide citation)

A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memo ...


3
Ely K Tsern, Thomas J Holman, Richard M Barth, Andrew V Anderson, Paul G Davis, Craig E Hampel, Donald C Stark, Abhijit M Abhyankar: Memory device and system including a low power interface. Intel Corporation, Rambus, Pennie & Edmonds, April 23, 2002: US06378018 (113 worldwide citation)

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power inte ...


4
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: High performance cost optimized memory. Rambus Incorporated, Pennie & Edmonds, June 4, 2002: US06401167 (94 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...


5
Paul G Davis, Frederick A Ware, Craig E Hampel: Method and apparatus for two step memory write operations. Rambus, Pennie & Edmonds, January 29, 2002: US06343352 (81 worldwide citation)

A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for th ...


6
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: Dram core refresh with reduced spike current. Rambus, Pennie & Edmonds, June 13, 2000: US06075744 (75 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...


7
Jared LeVan Zerbe, Michael Tak kei Ching, Abhijit M Abhyankar, Richard M Barth, Andy Peng Pui Chan, Paul G Davis, William F Stonecypher: Method and apparatus for fail-safe resynchronization with minimum latency. Rambus Incorporated, Pennie & Edmonds, October 29, 2002: US06473439 (65 worldwide citation)

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization ...


8
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: DRAM core refresh with reduced spike current. Rambus, Pennie & Edmonds, July 24, 2001: US06266292 (64 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...


9
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: DRAM core refresh with reduced spike current. Rambus, Pennie & Edmonds, July 22, 2003: US06597616 (63 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...


10
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: DRAM core refresh with reduced spike current. Rambus, Pennie & Edmonds, January 29, 2002: US06343042 (63 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...