1
Oscar Frederick Jones Jr: Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture. United Memories, Sony Corporation, William J Kubida, Peter J Meza, Hogan & Hartson, September 16, 2003: US06622198 (63 worldwide citation)

A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. T ...


2
Jim L Rogers, Steven W Tomashot, David W Bondurant, Oscar Frederick Jones Jr, Kenneth J Mobley: Cached synchronous DRAM architecture having a mode register programmable cache policy. International Business Machines, Francis J Thornton, Robert A Walsh, September 11, 2001: US06289413 (59 worldwide citation)

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode ...


3
Ronald H Sartore, Kenneth J Mobley, Donald G Carrigan, Oscar Frederick Jones Jr: Enhanced DRAM with single row SRAM cache for all device read operations. Ramtron International Corporation, William J Kubida Esq, Richard A Bachand Esq, Peter J Meza Esq, February 24, 1998: US05721862 (58 worldwide citation)

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data ...


4
Michael C Parris, Oscar Frederick Jones Jr: Data inversion register technique for integrated circuit memory testing. United Memories, Sony Corporation, William J Kubida, Peter J Meza, Hogan & Hartson, December 8, 2009: US07631233 (13 worldwide citation)

A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined in ...


5
Oscar Frederick Jones Jr: Clock controlled power-down state. United Memories, Sony Corporation, Peter J Meza, William J Kubida, Hogan & Hartson, September 7, 2004: US06788122 (12 worldwide citation)

A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle latches in conjunction with alternate power-gated circuitry, even when many stages are cascaded in a pipelin ...


6
Oscar Frederick Jones Jr, Michael C Parris: Simultaneous function dynamic random access memory device technique. United Memories, Sony Corporation, William J Kubida, Peter J Meza, Hogan & Hartson, November 4, 2003: US06643212 (11 worldwide citation)

A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock ...


7
Oscar Frederick Jones Jr: Refresh initiated precharge technique for dynamic random access memory arrays using look-ahead refresh. United Memories, Sony Corporation, William J Kubida, Hogan & Hartson, December 23, 2003: US06667927 (10 worldwide citation)

A refresh initiated precharge technique using look-ahead refresh eliminates the need to close banks in a dynamic random access memory (“DRAM”) array prior to executing a “refresh” command by taking advantage of the fact that the actual initiation of an internal “refresh” operation is delayed by at l ...


8
Michael C Parris, Douglas Blaine Butler, Kim C Hardee, Oscar Frederick Jones Jr: Non-contiguous masked refresh for an integrated circuit memory. United Memories, Sony Corporation, Peter J Meza, William J Kubida, Hogan & Hartson, June 28, 2005: US06912168 (8 worldwide citation)

A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which shou ...


9
Oscar Frederick Jones Jr, Michael C Parris: Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry. United Memories, Sony Corporation, William J Kubida, Peter J Meza, Hogan & Hartson, May 4, 2004: US06732305 (7 worldwide citation)

An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform ...


10
Michael C Parris, Douglas Blaine Butler, Oscar Frederick Jones Jr: Dual word line mode for DRAMs. United Memories, Sony Corporation, Peter J Meza, William J Kubida, Hogan & Hartson, February 21, 2006: US07002874 (6 worldwide citation)

An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a wo ...