1
Linda J Rankin, Joseph Bonasera, Nitin Y Borkar, Linda C Ernst, Suvansh K Kapur, Daniel A Manseau, Frank Verhoorn: Method and apparatus for providing remote memory access in a distributed memory multiprocessor system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 18, 1997: US05613071 (130 worldwide citation)

A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the ...


2
Sriram R Vangal, Yatin Hoskote, Nitin Y Borkar, Jianping Xu, Vasantha K Erraguntla, Shekhar Y Borkar: Network protocol engine. Intel Corporation, Robert A Greenberg, February 20, 2007: US07181544 (41 worldwide citation)

Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.


3
Manpreet S Khaira, Nitin Y Borkar: Conditional carry scheduler for round robin scheduling. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 18, 1994: US05357512 (35 worldwide citation)

A conditional carry scheduling unit that performs a scheduler carry operation for a round robin scheduler that schedules communication among a plurality of clients who compete to use a shared resource. Each client asserts a request bit to request use of the shared resource, and receives a grant bit ...


4
Linda J Rankin, Paul R Pierce, Gregory E Dermer, Wen Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y Borkar: Scalable distributed memory and I/O multiprocessor system. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, June 6, 2006: US07058750 (22 worldwide citation)

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send an ...


5
Yatin Hoskote, Sriram R Vangal, Vasantha K Erraguntla, Nitin Y Borkar: Hardware-based multi-threading for packet processing. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 23, 2010: US07668165 (14 worldwide citation)

Methods and apparatus for processing transmission control protocol (TCP) packets using hardware-based multi-threading techniques. Inbound and outbound TCP packet are processed using a multi-threaded TCP offload engine (TOE). The TOE includes an execution core comprising a processing engine, a schedu ...


6
Linda J Rankin, Paul R Pierce, Gregory E Dermer, Wen Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y Borkar: Scalable distributed memory and I/O multiprocessor systems and associated methods. Intel Corporation, Schwegman Lundberg & Woessner P A, March 11, 2008: US07343442 (7 worldwide citation)

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send an ...


7
Rajendran Nair, Gregory E Dermer, Stephen R Mooney, Nitin Y Borkar: Low jitter external clocking. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, September 28, 2004: US06798265 (6 worldwide citation)

A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second cl ...


8
Rajendran Nair, Gregory E Dermer, Stephen R Mooney, Nitin Y Borkar: Low jitter external clocking. Inter Corporation, Schwegman Lundberg Woessner & Kluth P A, June 25, 2002: US06411151 (6 worldwide citation)

A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second cl ...


9
Linda J Rankin, Paul R Pierce, Gregory E Dermer, Wen Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y Borkar: Scalable memory and I/O multiprocessor systems. Intel Corporation, Guojun Zhou, April 19, 2011: US07930464 (5 worldwide citation)

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send an ...


10
Sriram R Vangal, Yatin Hoskote, Nitin Y Borkar, Jianping Xu, Vasantha K Erraguntla, Shekhar Y Borkar: Packet-based clock signal. Intel Corporation, Robert A Greenberg, March 21, 2006: US07016354 (5 worldwide citation)

In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that proces ...