1
James M Brayton, Michael W Rhodehamel, Nitin V Sarangdhar, Glenn J Hinton: Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 22, 1997: US05623628 (137 worldwide citation)

A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate t ...


2
Nitin V Sarangdhar, Dave Papworth, P K Nizar, David G Carson: Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 25, 1995: US05410710 (79 worldwide citation)

A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a ...


3
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Michael W Rhodehamel, Matthew A Fisch: Computer system with distributed bus arbitration scheme for symmetric and priority agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 3, 1996: US05581782 (66 worldwide citation)

A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a rou ...


4
Nitin V Sarangdhar, P K Nizar, David G Carson: Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 10, 1996: US05555420 (58 worldwide citation)

A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadca ...


5
Nitin V Sarangdhar, Konrad K Lai: Apparatus and method for performing error correction in a multi-processor system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 27, 1996: US05550988 (57 worldwide citation)

In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the ...


6
Nitin V Sarangdhar, Wen Hann Wang, Matthew Fisch: Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 27, 1996: US05551005 (55 worldwide citation)

In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, o ...


7
Wen Hann Wang, Konrad K Lai, Gurbir Singh, Mandar S Joshi, Nitin V Sarangdhar, Matthew A Fisch: Apparatus and method for caching lock conditions in a multi-processor system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 21, 1999: US06006299 (50 worldwide citation)

In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A ...


8
Mandar S Joshi, Andrew F Glew, Nitin V Sarangdhar: Write combining buffer for sequentially addressed partial line operations originating from a single instruction. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 13, 1997: US05630075 (46 worldwide citation)

A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for combining data of at least two write commands into a single data set, wherein the combined data set is tran ...


9
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Peter D MacWilliams, Stephen S Pawlowski, Michael W Rhodehamel: Method and apparatus for performing deferred transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 25, 1997: US05615343 (39 worldwide citation)

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents an ...


10
Gurbir Singh, Wen Hann Wang, Michael W Rhodehamel, John M Bauer, Nitin V Sarangdhar: Method and apparatus for cache memory replacement line identification. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 15, 1998: US05809524 (33 worldwide citation)

A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers request ...