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Rebecca L Stamm, R Iris Bahar, Michael Callander, Linda Chao, Derrick R Meyer, Douglas Sanders, Richard L Sites, Raymond Strouble, Nicholas Wade: Error transition mode for multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, October 13, 1992: US05155843 (106 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth ...


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Nicholas Wade, Mark Lalich, Bruce Young: Method and apparatus for providing deterministic read access to main memory in a computer system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 18, 1997: US05613075 (68 worldwide citation)

A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a sel ...


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Ken M Crocker, Radhakrishnan Venkataraman, Nicholas Wade: Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 22, 1999: US05915265 (14 worldwide citation)

A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If a ...


4
Ken M Crocker, Radhakrishnan Venkataraman, Nicholas Wade: Method and apparatus to permit the boot of a shared memory buffer architecture employing an arbitrary operating system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 4, 1998: US05790849 (11 worldwide citation)

A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and d ...


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Ken M Crocker, Radhakrishnan Venkataraman, Nicholas Wade: Method and apparatus for dynamically resizing a frame buffer in a shared memory buffer architecture system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 14, 1999: US05953746 (9 worldwide citation)

A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If a ...


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Andy E Hooper, Nicholas Wade Clyde: Backside stealth dicing through tape followed by front side laser ablation dicing process. Micron Technology, Parsons Behle & Latimer, September 18, 2018: US10079169

A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with ...


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