1
Nicholas J Szluk: Totally self-aligned CMOS process. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, October 20, 1987: US04701423 (66 worldwide citation)

A CMOS process incorporates self-aligned buried contacts, lightly doped source/drain structures, and sidewall oxide spacers. The process is tailored so that individual process steps and structural features serve several functions, thereby providing the desirable structural features and small geometr ...


2
Nicholas J Szluk, Werner A Metz Jr, Gayle W Miller, Maurice M Moll: Programmable read only memory using a tungsten fuse. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, March 3, 1987: US04647340 (41 worldwide citation)

An electrically programmable memory cell using selectively deposited tungsten on a sidewall to define a fuse region. Fabrication of the fuse structure involves only a single mask departure from standard MOSFET processing during which a selective isotropic etch of a silicon nitride sidewall structure ...


3
Nicholas J Szluk, Gayle W Miller: Process for forming LDD MOS/CMOS structures. NCR Corporation, J T Cavender, Casimer K Salys, November 3, 1987: US04703551 (40 worldwide citation)

A process for selectively forming NMOS/PMOS/CMOS integrated circuits and for selectively incorporating any or all of lightly doped drain-source (LDD) regions, sidewall gate oxide structures, and guard band regions.


4
Werner A Metz Jr, Nicholas J Szluk, Gayle W Miller, Michael J Drury, Paul A Sullivan: Use of selectively deposited tungsten for contact formation and shunting metallization. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, March 10, 1987: US04648175 (36 worldwide citation)

A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed field effect devices using contacts through the dielectric layer. A thin layer of intrinsic polysilicon ...


5
Gayle W Miller, Nicholas J Szluk, William W McKinley, Hubert O Hayworth, George Maheras: Fabrication process for aligned and stacked CMOS devices. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, March 31, 1987: US04654121 (31 worldwide citation)

A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regio ...


6
Gayle W Miller, Nicholas J Szluk, George Maheras, Werner A Metz Jr: MOSFET process using implantation through silicon. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, July 28, 1987: US04682404 (17 worldwide citation)

A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Ligh ...


7
Nicholas J Szluk, Gayle W Miller: Formation of self-aligned stacked CMOS structures by lift-off. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, July 14, 1987: US04679299 (15 worldwide citation)

A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the struc ...


8
Nicholas J Szluk, Jay T Fukumoto: Method of making CMOS integrated devices in seeded islands. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, March 5, 1991: US04997780 (15 worldwide citation)

The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a la ...


9
Nicholas J Szluk, Jay T Fukumoto: CMOS integrated devices in seeded islands. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, January 17, 1989: US04799097 (10 worldwide citation)

The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a la ...