1
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Craig S Sander, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Forming local interconnects in integrated circuits. Advanced Micro Devices, Foley & Lardner, April 18, 2000: US06051881 (13 worldwide citation)

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect ...


2
Jeremy I Martin, Nicholas J Kepler, Larry L Zhao: Method and test structure for characterizing sidewall damage in a semiconductor device. Advanced Micro Devices, Williams Morgan & Amerson P C, July 29, 2003: US06600333 (11 worldwide citation)

A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and se ...


3
Paul R Besser, Christian Zistl, Nicholas J Kepler: Method of forming a semiconductor device with metal silicide regions. Advanced Micro Devices, Williams Morgan & Amerson P C, July 31, 2001: US06268255 (9 worldwide citation)

The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion ...


4
Craig S Sander, Rich K Klein, Asim A Selcuk, Nicholas J Kepler, Christoper A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Minimizing transistor size in integrated circuits. Advanced Micro Devices, Foley & Lardner, April 11, 2006: US07026691 (4 worldwide citation)

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate ...


5
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Forming minimal size spaces in integrated circuit conductive lines. Advanced Micro Devices, Foley & Lardner, February 20, 2001: US06191034 (4 worldwide citation)

A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a redu ...


6
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Craig S Sander, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Method for self-aligning polysilicon gates with field isolation and the resultant structure. Advanced Micro Devices, Foley & Lardner, April 4, 2000: US06046088 (4 worldwide citation)

A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequent ...


7
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Forming minimal size spaces in integrated circuit conductive lines. Advanced MicroDevices, Foley & Lardner, July 27, 1999: US05930659 (2 worldwide citation)

A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to ...


8
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Craig S Sander, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Minimizing transistor size in integrated circuits. Advanced Micro Devices, Foley & Lardner, November 14, 2000: US06146954 (2 worldwide citation)

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects pr ...


9
Srikanteswara Dakshina Murthy, Paul R Besser, Jonathan B Smith, Eric M Apelgren, Christian Zistl, Jeremy I Martin, Lie Larry Zhao, Nicholas J Kepler: Method of defining small openings in dielectric layers. Advanced Micro Devices, Williams Morgan & Amerson P C, June 18, 2002: US06406993 (2 worldwide citation)

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method fur ...


10
Christian Zistl, Paul R Besser, Eric M Apelgren, Nicholas J Kepler, Srikanteswara Dakshina Murthy: Semiconductor device with partial passivation layer. Advanced Micro Devices, Williams Morgan & Amerson P C, November 6, 2001: US06313538 (1 worldwide citation)

A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer ...