1
Nicholas G Samra, Betty Y Kikuta: Method and apparatus for processing multiple cache misses using reload folding and store merging. Motorola, Paul J Polansky, September 15, 1998: US05809530 (102 worldwide citation)

A data processor (40) keeps track of misses to a cache (71) so that multiple misses within the same cache line can be merged or folded at reload time. A load/store unit (60) includes a completed store queue (61) for presenting store requests to the cache (71) in order. If a store request misses in t ...


2
Nicholas G Samra: Content addressable memory system. Motorola, Lee E Chastain, July 8, 1997: US05646878 (69 worldwide citation)

A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the data set stored in the CAM cell associated with ...


3
Nicholas G Samra, Stephen J Jourdan: Intra-instruction fusion. Intel Corporation, Erik M Metzger, May 23, 2006: US07051190 (20 worldwide citation)

Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in paral ...


4
Nicholas G Samra, Jacob Doweck: Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 6, 2003: US06560671 (20 worldwide citation)

An apparatus, system and method for accelerating exchange (XCHG) instructions in a processor using a register alias table (RAT) data array and a content addressable memory (CAM) to handle register renaming. The RAT has at least one read port, at least one write port, and a plurality of address entri ...


5
Jacqueline S Nelson, Nicholas G Samra: Method of speculatively executing store instructions prior to performing snoop operations. Motorola, June 9, 1998: US05765208 (17 worldwide citation)

A data processor (10) has a load/store unit (28) that executes store-to-shared-data instructions before it exclusively owns the data designated by the instruction. Later, a bus interface unit (12) performs a snoop transaction to obtain exclusive ownership of the data. If data processor successfully ...


6
Nicholas G Samra, Jacob Doweck, Belliappa Kuttanna: Dual state rename recovery using register usage. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 22, 2002: US06470435 (11 worldwide citation)

An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent regist ...


7
Nicholas G Samra, Stephan J Jourdan, David J Sager, Glenn J Hinton: Fusing load and alu operations. Intel Corporation, Erik M Metzger, July 8, 2008: US07398372 (6 worldwide citation)

Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memor ...


8
Nicholas G Samra, Andrew S Huang: Virtual multithreading translation mechanism including retrofit capability. Intel Corporation, Trop Pruner & Hu P C, February 23, 2010: US07669203 (5 worldwide citation)

Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that uti ...


9
Nicholas G Samra, Murali S Chinnakonda: Method and apparatus for fast dependency coordinate matching. Intel Corporation, Larry M Mennemeier, May 3, 2005: US06889314 (5 worldwide citation)

Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coor ...


10
Nicholas G Samra, Andrew S Huang, Namratha R Jaisimha: Methods and apparatus to control functional blocks within a processor. Intel Corporation, Hanley Flight & Zimmerman, July 17, 2007: US07246219 (5 worldwide citation)

Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blo ...