1
Rebecca L Stamm, Ruth I Bahar, Raymond L Strouble, Nicholas D Wade, John H Edmondson: Ensuring write ordering under writeback cache error conditions. Digital Equipment Corporation, Arnold White & Durkee, September 13, 1994: US05347648 (118 worldwide citation)

Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that p ...


2
Rebecca L Stamm, Nicholas D Wade: Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, April 4, 1995: US05404482 (116 worldwide citation)

A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content a ...


3
Nicholas D Wade: Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 25, 1997: US05606672 (95 worldwide citation)

An apparatus and method for connecting a bus bridge to a plurality of bus interfaces. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly ...


4
Rebecca L Stamm, Ruth I Bahar, Nicholas D Wade: Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, April 4, 1995: US05404483 (71 worldwide citation)

A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the ca ...


5
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparatus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 29, 2000: US06112016 (65 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


6
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparartus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1998: US05822767 (46 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


7
Gary A Solomon, Peter D MacWilliams, George R Hayek, Nicholas D Wade, Abid Asghar: Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 29, 1997: US05625779 (37 worldwide citation)

An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for ...


8
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Scalable cache attributes for an input/output bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 22, 1997: US05651137 (30 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


9
Nicholas D Wade: Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 27, 1998: US05828854 (28 worldwide citation)

An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are conne ...


10
Jeffrey L Rabe, Nicholas D Wade, Bruce Young: Deadlock avoidance mechanism and method for multiple bus topology. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 10, 1998: US05717873 (21 worldwide citation)

Apparatus and a method for eliminating deadlock in a multibus computer system which system includes a primary bus, and a secondary bus, a bridge circuit for joining the primary bus to a bus master, and a second bridge circuit for joining the primary bus to the secondary bus. The invention causes the ...