Bowden Iii Raymond D, Nibby Chester M Jr: Burst read address generation.. Bull Hn Information Syst, April 7, 1993: EP0535670-A1 (38 worldwide citation)

A memory system couples to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes means for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of the set of ...


Johnson Robert B, Nibby Chester M Jr, Moore Dana W: Memory system.. Honeywell Inf Systems, July 15, 1981: EP0032136-A2 (9 worldwide citation)

A memory system comprises a plurality of rows (RASO-RAS7) of memory chips, 22 chips per row (for 22-bit words). Each chip contains 64K bits, giving 64K words per row. The least significant bits (bits 21 and 22) of the word address select the row of chips, so that successive word addresses are in suc ...



Barlow George J, Keeley James W, Nibby Chester M Jr: Cache memory resiliency in processing a variety of address faults.. Honeywell Bull, January 25, 1989: EP0300166-A2 (4 worldwide citation)

A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsyst ...



Keeley James W, Petry Keith L, Lemay Richard A, Hirsch Thomas S, Nibby Chester M Jr: Power-up sequence system.. Bull Hn Information Syst, April 21, 1993: EP0537688-A2 (3 worldwide citation)

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmab ...

Peters Arthur, Zelley Richard C, Carroll Elmer W, Barlow George J, Nibby Chester M Jr, Keeley James W: Data processing system having a bus command generated by one subsystem on behalf of another subsystem.. Honeywell Bull, June 29, 1988: EP0272547-A2 (3 worldwide citation)

A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field ...