1
Albert Fazio, Gregory E Atwood, Neal R Mielke: Floating gate non-volatile memory with blocks and memory refresh. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 24, 1993: US05239505 (92 worldwide citation)

A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. ...


2
Gregory E Atwood, Owen W Jungroth, Neal R Mielke, Branislav Vajdic: Single cell reference scheme for flash memory sensing and program state verification. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 31, 1995: US05386388 (86 worldwide citation)

A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single c ...


3
Stephen F Sullivan, Neal R Mielke: Flash erasable single poly EPROM device. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 5, 1994: US05301150 (62 worldwide citation)

A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor substrate as the control gate. One plate of the capacitor is formed from the same polysilicon layer as the flo ...


4
Albert Fazio, Gregory E Atwood, Neal R Mielke, Alan E Baker: Floating gate non-volatile memory blocks and select transistors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 14, 1993: US05245570 (62 worldwide citation)

A non-volatile memory device is described. The memory device includes a global bit line, a first block, and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate and a control gate. A first word line is coupled to the control gate of the ...


5
Krishna Seshan, Neal R Mielke: Planar guard ring. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 24, 2000: US06137155 (28 worldwide citation)

An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer for ...


6
Neal R Mielke: Method of screening EPROM-related devices for endurance failure. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 16, 1990: US04963825 (19 worldwide citation)

A method for screening EPROM-related integrated circuits for endurance failure is described. The screening method is based on a measurement of the number and distribution of cells within the EPROM-related device which program and/or erase significantly further and faster than "normal" cells. The era ...


7
Neal R Mielke: Compensation circuit for leakage in flash EPROM. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 15, 1993: US05220528 (18 worldwide citation)

An improvement in a memory array using single device floating gate flash memory cells for compensating for drain leakage. Drain leakage can cause hot hole injection during erasing thereby over-erasing a cell causing it to act as a depletion device. The column line is biased during erasing, raising t ...


8
Krishna Seshan, Neal R Mielke: Planar guard ring. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 23, 2002: US06376899 (6 worldwide citation)

An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer for ...


9
Krishna Seshan, Neal R Mielke: Metal staples to prevent interlayer delamination. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 2, 1999: US05977639 (5 worldwide citation)

The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The ...


10
Jerry G Jex, Neal R Mielke: Protected erase voltage discharge transistor in a nonvolatile semiconductor memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 3, 1994: US05309012 (5 worldwide citation)

A semiconductor memory having a memory cell for storing a bit of data and a pull-down transistor for coupling the source of the memory cell to ground in order to read the memory cell. The pull-down transistor is comprised of a polysilicon gate coupled to a control means for switching the transistor ...