1
Narbeh Derhacobian, Hao Fang: Method for reducing program disturb during self-boosting in a NAND flash memory. Advanced Micro Devices, November 23, 1999: US05991202 (174 worldwide citation)

A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a pl ...


2
Narbeh Derhacobian, Shane C Hollmer, Ravi S Sunkavalli: Method of maintaining constant erasing speeds for non-volatile memory cells. Advanced Micro Devices, Brinks Hofer Gilson & Lione, April 10, 2001: US06215702 (148 worldwide citation)

A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region ...


3
Narbeh Derhacobian, Janet S Y Wang, Daniel Sobek, Sameer S Haddad: Method of programming a non-volatile memory cell using a current limiter. Advanced Micro Devices, Brinks Hofer Gilson & Lione, July 31, 2001: US06269023 (127 worldwide citation)

A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current l ...


4
Darlene G Hamilton, Janet S Y Wang, Narbeh Derhacobian, Tim Thurgate, Michael K Han: Charge injection. Advanced Micro Devices, Amin & Turocy, May 20, 2003: US06567303 (73 worldwide citation)

A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresse ...


5
Mark T Ramsbey, Jean Y Yang, Hidehiko Shiraiwa, Michael A Van Buskirk, David M Rogers, Ravi S Sunkavalli, Janet S Wang, Narbeh Derhacobian: Planar structure for non-volatile memory devices. Advanced Micro Devices, Fujitsu, Amin & Turocy, April 1, 2003: US06541816 (72 worldwide citation)

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate ...


6
Darlene G Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli, Narbeh Derhacobian: Tailored erase method using higher program VT and higher negative gate erase. Advanced Micro Devices, Amin & Turocy, August 27, 2002: US06442074 (68 worldwide citation)

A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase ...


7
Darlene G Hamilton, Narbeh Derhacobian, Janet S Y Wang, Kulachet Tanpairoj: Higher program VT and faster programming rates based on improved erase methods. Advanced Micro Devices, Amin & Turocy, July 8, 2003: US06590811 (67 worldwide citation)

A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperat ...


8
Janet S Y Wang, Narbeh Derhacobian: Method of programming a non-volatile memory cell using a baking process. Advanced Micro Devices, Amin & Turocy, September 9, 2003: US06618290 (66 worldwide citation)

A method of programming that includes programming a fresh memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. Baking the programmed fresh cell caus ...


9
Darlene G Hamilton, Narbeh Derhacobian, Kulachet Tanpairoj, Ravi Sunkavalli: Negative gate erase. Advanced Micro Devices, Amin & Turocy L, October 23, 2001: US06307784 (54 worldwide citation)

A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire a ...


10
Michael Han, Narbeh Derhacobian: NAND array structure and method with buried layer. Advanced Micro Devices, Skjerven Morrill, March 4, 2003: US06529410 (49 worldwide citation)

An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell duri ...



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