1
Akira Kabemoto, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura, Hirohide Sugahara, Junji Nishioka, Takatsugu Sasaki, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Hiroaki Ishihata, Takeshi Horie, Toshiyuki Shimizu: Coherence apparatus for cache of multiprocessor. Fujitsu, PFU, Staas & Halsey, March 30, 1999: US05890217 (61 worldwide citation)

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using t ...


2
Hisayuki Nishimura, Shigeru Honda, Naohiro Shibata: Circuit mounting unit. Fujitsu, Armstrong Westerman Hattori McLeland & Naughton, October 7, 1997: US05675467 (36 worldwide citation)

The present invention relates to a circuit mounting unit that can prevent a voltage drop and noise occurrence due to current inflow at the time of a hot insertion or withdrawal operation without mounting a capacitor with large capacitance on the side of a main unit. The circuit mounting unit include ...


3
Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura: Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system. Fujitsu, PFU, Armstrong Westerman Hattori McLeland & Naughton, March 14, 2000: US06038674 (8 worldwide citation)

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control un ...