1
Richard R Garnache, Donald M Kenney, Nandor G Thoma: V-MOS Device with self-aligned multiple electrodes. International Business Machines Corporation, Howard J Walter Jr, December 14, 1982: US04364074 (41 worldwide citation)

High density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which ...


2
Humberto F Casal, Rafey Mahmud, Trong Nguyen, Mark L Shulman, Nandor G Thoma: Symmetric clock system for a data processing system including dynamically switchable frequency divider. International Business Machines Corporation, Anthony V S Jenkens & Gilchrist England, June 4, 1996: US05524035 (22 worldwide citation)

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even div ...


3
Wayne R Kraft, Victor S Moore, William L Stahl Jr, Nandor G Thoma: Bus line precharging tristate driver circuit. International Business Machines Corporation, Richard E Bee, July 23, 1985: US04531068 (22 worldwide citation)

A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output co ...


4
Peter Juergen Klim, Nandor G Thoma: High speed pipeline method and apparatus. International Business Machines Corporation, Anthony V S England, March 24, 1998: US05732233 (21 worldwide citation)

A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and ...


5
Humberto F Casal, Joel R Davidson, Hehching H Li, Yuan C Lo, Trong D Nguyen, Campbell H Snyder, Nandor G Thoma: Hierarchical clocking system using adaptive feedback. International Business Machines, Laurence R Letson, April 8, 1997: US05619158 (17 worldwide citation)

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase al ...


6
Nandor G Thoma, Scott E Doyle: Single-event upset tolerant latch for sense amplifiers. BAE Systems Information and Electronic Systems Integration, Anthony P Ng, Bracewell & Patterson L, November 26, 2002: US06487134 (16 worldwide citation)

A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and ...


7
Tai Cao, Satyajit Dutta, Thai Q Nguyen, Nandor G Thoma, Thanh D Trinh: CMOS receiver circuit. International Business Machines Corporation, Kelly K Winstead Sechrest & Minick Kordzik, Mark E McBurney, July 23, 1996: US05539333 (13 worldwide citation)

A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver c ...


8
Gerard A Veneski, Nandor G Thoma, Moises Cases: Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit. International Business Machines, Richard E Bee, March 11, 1986: US04575794 (13 worldwide citation)

A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable log ...


9
James W Davis, Victor S Moore, Nandor G Thoma: Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design. International Business Machines Corporation, August 26, 1986: US04608649 (11 worldwide citation)

A topological physical circuit design is utilized for the support of a Differential Cascode Voltage Switch circuit/logic technology in an Automated Placement-Wiring environment. This physical entity takes the form of a "brickwall" set of transistors in a Master Slice image which may be stored and la ...


10
Jacquelin Babakanian, James W Davis, Mark S Garvin, Robert M Swanson, Nandor G Thoma, David M Wu: Fully testable DCVS circuits with single-track global wiring. International Business Machines, Romualdas Strimaitis, John C Smith, March 29, 1994: US05299136 (11 worldwide citation)

Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is config ...