1
Richard D Muratori, Myles J Wilde, Donald F Hooper: Graphical user interface that displays operation of processor threads over time. Intel Corporation, Fish & Richardson P C, August 26, 2003: US06611276 (105 worldwide citation)

A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding ...


2
Hugh M Wilkinson III, Matthew J Adiletta, Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section. Intel Corporation, Fish & Richardson P C, August 23, 2005: US06934951 (35 worldwide citation)

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engine ...


3
Donald F Hooper, Myles J Wilde, Matthew J Adiletta, Gilbert Wolrich: Flow control in a network environment. Intel Corporation, Fish & Richardson P C, October 7, 2008: US07433307 (22 worldwide citation)

Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.


4
Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein, Myles J Wilde, Matthew J Adiletta: Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms. Intel Corporation, Fish & Richardson P C, May 29, 2007: US07225281 (9 worldwide citation)

A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing o ...


5
Hugh M Wilkinson III, Matthew J Adiletta, Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access. Intel Corporation, Fish & Richardson P C, November 27, 2007: US07302549 (9 worldwide citation)

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning ...


6
Richard D Muratori, Myles J Wilde, Donald F Hooper: Graphical user interface. Intel Corporation, Fish & Richardson P C, March 11, 2008: US07343563 (5 worldwide citation)

A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding ...


7
Donald F Hooper, Hugh Wilkinson, Mark Rosenbluth, Debra Bernstein, Michael F Fallon, Sanjeev Jain, Myles J Wilde, Gilbert M Wolrich: Folding for a multi-threaded network processor. Intel Corporation, Daly Crowley Mofford & Durkee, July 3, 2007: US07240164 (5 worldwide citation)

A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple ...


8
Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Signal aggregation. Intel Corporation, Fish & Richardson P C, May 20, 2008: US07376950 (1 worldwide citation)

The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operation.


9
Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein, Myles J Wilde, Matthew J Adiletta: Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms. Fish & Richardson PC, June 5, 2003: US20030105899-A1 (1 worldwide citation)

A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing o ...


10
Michael F Fallon, Myles J Wilde, Matthew Adiletta, Paul H Dormitzer: Printing information on electronic paper. Intel Corporation, International IP Law Group P L L C, March 1, 2016: US09272537

A method and system for displaying information on an electronic paper (or “e-paper”) is included herein. The method includes passing the e-paper through an e-paper printer. Additionally, the method includes changing a status of a pixel on the e-paper.