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Edward Grochowski, John Shen, Hong Wang, Doron Orenstein, Gad S Sheaffer, Ronny Ronen, Murali M Annavaram: Method and apparatus for varying energy per instruction according to the amount of available parallelism. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 14, 2008: US07437581 (70 worldwide citation)

A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the va ...


2
Bryan Black, Murali M Annavaram, Donald W McCauley, John P Devale: Prefetching from dynamic random access memory to a static random access memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 4, 2011: US08032711 (37 worldwide citation)

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch l ...


3
Murali M Annavaram, Trung A Diep, John Shen: Method and apparatus for variable pop hardware return address stack. Dennis A Nicholls, Blakely Sokoloff Taylor & Zafman, March 11, 2004: US20040049666-A1

A system and method for correcting a hardware return address stack is disclosed. A set of digital comparators examines several locations near the top of the stack and compares them with a calculated return address. If a match is detected, the slot number corresponding to the match is overwritten int ...


4
Bryan Black, Murali M Annavaram, Donald W McCauley, John P Devale: Prefetching from dynamic random access memory to a static random access memory. Intel Corporation, Intel Corporation, c o INTELLEVATE, June 26, 2008: US20080155196-A1

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch l ...


5
Edward Grochowski, John Shen, Hong Wang, Doron Orenstein, Gad S Sheaffer, Ronny Ronen, Murali M Annavaram: Method and apparatus for varying energy per instruction according to the amount of available parallelism. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 4, 2006: US20060095807-A1

A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the va ...


6