1
David Allon, Moshe Bach, Yosef Moatti, Abraham Teperman: Load balancing of network by maintaining in each computer information regarding current load on the computer and load on some other computers in the network. International Business Machines Corporation, James C Pintner, July 23, 1996: US05539883 (185 worldwide citation)

A method is described of operating a computer in a network of computers using an improved load balancing technique. Logical links are generated between the computer and other computers in the network so that a tree structure is formed, the computer being logically linked to one computer higher up th ...


2
Ali Reza Adl Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V Olivier, Bratin Saha, Ady Tal, Adam Wele: Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system. Intel Corporation, Barnes & Thornburg, October 8, 2013: US08555016 (3 worldwide citation)

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barr ...


3
Ali Reza Adl Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V Olivier, Bratin Saha, Ady Tal, Adam Welc: Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system. Intel Corporation, Barnes & Thornburg, June 9, 2015: US09052947 (1 worldwide citation)

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barr ...


4
Ali Reza Adl Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V Olivier, Bratin Saha, Ady Tal, Adam Wele: Unified optimistic and pessimistic concurrency control for a software transactional memory (stm) system. Intel Corporation, c o CPA Global, June 17, 2010: US20100153953-A1

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barr ...