1
Ming T Miu, John J Bradley: Program counter stacking method and apparatus for nested subroutines and interrupts. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, December 11, 1984: US04488227 (99 worldwide citation)

A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present rou ...


2
Ming T Miu, Virendra S Negi, Richard A Lemay: Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus. Honeywell Information Systems, John S Solakian, Ronald T Reiling, Nicholas Prasinos, September 20, 1977: US04050097 (93 worldwide citation)

Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock c ...


3
Thomas F Joyce, Ming T Miu, Jian Kuo Shen, Forrest M Phillips: Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page. Honeywell Bull, Faith F Driscoll, John S Solakian, November 15, 1988: US04785398 (61 worldwide citation)

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user ...


4
William Panepinto Jr, Ming T Miu, Chester M Nibby Jr, Jian Kuo Shen: Data processing system having centralized memory refresh. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, February 23, 1982: US04317169 (40 worldwide citation)

In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory re ...


5
Theodore R Staplin Jr, John J Bradley, Richard L King, Robert C Miller, Ming T Miu, Jian Kuo Shen: Data processing system having synchronous bus wait/retry cycle. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, January 22, 1985: US04495571 (40 worldwide citation)

A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which en ...


6
John J Bradley, Robert C Miller, Ming T Miu, Jian Kuo Shen, Theodore R Staplin Jr: Data processing system having data multiplex control apparatus. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, November 10, 1981: US04300193 (37 worldwide citation)

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the c ...


7
Ming T Miu, John J Bradley, Jian Kuo Shen: Microprogrammed system having hardware interrupt apparatus. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, November 20, 1984: US04484271 (31 worldwide citation)

A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the c ...


8
Jian Kuo Shen, John J Bradley, Richard L King, Robert C Miller, Ming T Miu, Theodore R Staplin Jr: Data processing system having centralized data alignment for I/O controllers. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, Ronald T Reiling, March 23, 1982: US04321665 (25 worldwide citation)

In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align ...


9
Virendra S Negi, Ming T Miu: Data processing interrupt apparatus having selective suppression control. Honeywell Information Systems, Finnegan Henderson Farabow Garrett & Dunner, August 19, 1980: US04218739 (24 worldwide citation)

Interrupts generated within a data processor (internal interrupts) and an interrupt received from a peripheral device (external interrupts) coupled with the processor are prioritized and, unless suppressed, are coupled to generate an interrupt signal for use in addressing a routine for servicing the ...


10
John J Bradley, Thomas O Holtey, Robert C Miller, Ming T Miu, Jian Kuo Shen, Theodore R Staplin Jr: Data processing system having direct memory access bus cycle. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, Ronald T Reiling, October 6, 1981: US04293908 (21 worldwide citation)

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processi ...