1
Richard J Huang, Angela Hui, Robin Cheung, Mark Chang, Ming Ren Lin: Simplified dual damascene process for multi-level metallization and interconnection structure. Advanced Micro Devices, June 3, 1997: US05635423 (199 worldwide citation)

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer thereb ...


2
Ming Ren Lin, Jung Suk Goo, Haihong Wang, Qi Xiang: FinFET device incorporating strained silicon in the channel region. Advanced Micro Devices, Foley & Lardner, October 5, 2004: US06800910 (176 worldwide citation)

A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epi ...


3
Bin Yu, Ming Ren Lin, Shekhar Pramanick: Method of manufacturing a transistor with local insulator structure. Advanced Micro Devices, Foley & Lardner, April 30, 2002: US06380019 (110 worldwide citation)

A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet ...


4
Geoffrey Choh Fei Yeap, Qi Xiang, Ming Ren Lin: CMOS optimization method utilizing sacrificial sidewall spacer. Advanced Micro Devices, Mikio Ishimaru, July 25, 2000: US06093594 (107 worldwide citation)

An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and ...


5
Bin Yu, Ming Ren Lin, Shekhar Pramanick: Transistor with local insulator structure. Advanced Micro Devices, Foley & Lardner, December 30, 2003: US06670260 (96 worldwide citation)

A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet ...


6
Witold P Maszara, Srinath Krishnan, Ming Ren Lin: Fast Mosfet with low-doped source/drain. Advanced Micro Devices, Amin Eschweiler & Turocy, May 9, 2000: US06060364 (88 worldwide citation)

A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to for ...


7
Ming Ren Lin, Haihong Wang, Bin Yu: FinFET device with multiple fin structures. Advanced Micro Devices, Harrity & Snyder, July 13, 2004: US06762448 (88 worldwide citation)

A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin stru ...


8
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Self aligned via dual damascene. Advanced Micro Devices, Foley & Lardner, March 25, 1997: US05614765 (82 worldwide citation)

An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive li ...


9
Eric N Paton, Qi Xiang, Paul R Besser, Ming Ren Lin, Minh V Ngo, Haihong Wang: Mosfets incorporating nickel germanosilicided gate and methods for their formation. Advanced Micro Devices, Foley & Lardner, September 7, 2004: US06787864 (77 worldwide citation)

A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide pr ...


10
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Dual damascene with a sacrificial via fill. Advanced Micro Devices, Foley & Lardner, January 6, 1998: US05705430 (71 worldwide citation)

A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The ...



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