1
Min Yi Lin: Dual damascene interconnect structure with reduced parasitic capacitance. United Microelectronics, Winston Hsu, October 2, 2001: US06297554 (191 worldwide citation)

An improved structure of a dielectric layer between two adjacent copper wiring lines is disclosed. The dielectric layer is composed of silicon oxide and the adjacent copper wiring lines are formed using a dual damascene process. The structure of the dielectric layer according to the present inventio ...


2
Peng Yung Sung, An Min Chiang, Shau Tsung Yu, Min Yi Lin: Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer. Taiwan Semiconductor Manufacturing Company, George O Saile, Alek D Szecsy, July 29, 1997: US05652172 (8 worldwide citation)

A method for forming an aperture with a uniform void-free sidewall etch profile through a multi-layer insulator layer. There is formed upon a semiconductor substrate a multi-layer insulator layer which has a minimum of a first insulator layer and a second insulator layer. The second insulator layer ...