1
Fwu Iuan Hshieh, Brian H Floyd, Mike F Chang, Danny Nim, Daniel Ng: High density trench DMOS transistor with trench bottom implant. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, July 27, 1999: US05929481 (144 worldwide citation)

A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This trench bottom i ...


2
Fwu Iuan Hshieh, Mike F Chang, Kuo In Chen, Richard K Williams, Mohamed Darwish: High density trenched DMOS transistor. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, November 18, 1997: US05689128 (135 worldwide citation)

The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second ver ...


3
Mike F Chang, King Owyang, Fwu Iuan Hshieh, Yueh Se Ho, Jowei Dun: Surface mount and flip chip technology for total integrated circuit isolation. Siliconix Incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, May 26, 1998: US05757081 (114 worldwide citation)

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is att ...


4
Brian H Floyd, Dorman C Pitzer, Fwu Iuan Hshieh, Mike F Chang: Trenched field effect transistor with PN depletion barrier. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, June 29, 1999: US05917216 (102 worldwide citation)

A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ea ...


5
Fwu Iuan Hshieh, Mike F Chang, Yueh Se Ho, King Owyang: Trenched DMOS transistor having thick field oxide in termination region. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, November 26, 1996: US05578851 (100 worldwide citation)

A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (o ...


6
Fwu Iuan Hshieh, Mike F Chang, Lih Ying Ching, Sze H Ng, William Cook: Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness. Siliconix incorporated, May 13, 1997: US05629543 (100 worldwide citation)

A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. ...


7
Fwu Iuan Hshieh, Mike F Chang, Hamza Yilmaz: Method for fabricating a short channel trenched DMOS transistor. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, December 12, 1995: US05474943 (96 worldwide citation)

A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming ...


8
Fwu Iuan Hshieh, Mike F Chang, Yueh Se Ho, King Owyang: Trenched DMOS transistor fabrication having thick termination region oxide. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, June 17, 1997: US05639676 (94 worldwide citation)

A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (o ...


9
Mike F Chang, King Owyang, Fwu Iuan Hshieh, Yueh Se Ho, Jowei Dun: Surface mount and flip chip technology for total integrated circuit isolation. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, May 19, 1998: US05753529 (89 worldwide citation)

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is att ...


10
Brian H Floyd, Fwu Iuan Hshieh, Mike F Chang: Punch-through field effect transistor. Siliconix incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, January 7, 1997: US05592005 (87 worldwide citation)

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and d ...