1
Jun Zhao, Ashok Sinha, Avi Tepman, Mei Chang, Lee Luo, Alex Schreiber, Talex Sajoto, Stefan Wolff, Charles Dornfest, Michal Danek: Thermally floating pedestal collar in a chemical vapor deposition chamber. Applied Materials, Charles S Guenzer, Michael B Einschlag, December 8, 1998: US05846332 (183 worldwide citation)

A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material on peripheral portions of the pedestal sup ...


2
Robert Rozbicki, Michal Danek: Method for depositing a diffusion barrier for copper interconnect applications. Novellus Systems, Beyer Weaver & Thomas, July 20, 2004: US06764940 (77 worldwide citation)

Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portio ...


3
Jun Zhao, Ashok Sinha, Avi Tepman, Mei Chang, Lee Luo, Alex Schreiber, Talex Sajoto, Stefan Wolff, Charles Dornfest, Michal Danek: Apparatus for substrate processing with improved throughput and yield. Applied Materials, Townsend and Townsend and Crew, October 10, 2000: US06129044 (75 worldwide citation)

The present invention provides an approach which provides an increase in the number of usable substrates with a film, such as titanium nitride, deposited thereon at a sufficient deposition rate and where the film meets uniformity and resistivity specifications as well as providing good step coverage ...


4
Robert Rozbicki, Michal Danek, Erich Klawuhn: Method of depositing a diffusion barrier for copper interconnect applications. Novellus Systems, Beyer Weaver & Thomas, August 19, 2003: US06607977 (73 worldwide citation)

The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional ...


5
Gerard C D&apos Couto, George Tkach, Michael Woitge, Michal Danek: Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques. Novellus Systems, Kelly M Reynolds, DeLio & Peterson, January 6, 2004: US06673716 (66 worldwide citation)

A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with controlling the ...


6
Robert Rozbicki, Michal Danek: Barrier first method for single damascene trench applications. Novellus Systems, Beyer Weaver & Thomas, March 6, 2007: US07186648 (63 worldwide citation)

Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The sec ...


7
Robert Rozbicki, Michal Danek, Erich Klawuhn: Method of depositing copper seed on semiconductor substrates. Novellus Systems, Beyer Weaver & Thomas, November 4, 2003: US06642146 (58 worldwide citation)

The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substan ...


8
Tarek Suwwan de Felipe, Michal Danek, Erich Klawuhn, Alexander Dulkin: Deposition of conformal copper seed layers by control of barrier layer morphology. Novellus Systems, Beyer Weaver & Thomas, May 20, 2003: US06566246 (43 worldwide citation)

The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed ...


9
Gerard C D&apos Couto, George Tkach, Michal Danek: Use of RF biased ESC to influence the film properties of Ti and TiN. Novellus Systems, Kelly M Reynolds, DeLio & Peterson, November 25, 2003: US06652718 (42 worldwide citation)

A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings of 6:1 is disclosed. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination ...


10
Tarek Suwwan de Felipe, Michal Danek, Erich Klawuhn, Ronald A Powell: Method of depositing a diffusion barrier for copper interconnection applications. Novellus Systems, Beyer Weaver & Thomas, April 1, 2003: US06541374 (42 worldwide citation)

The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and die ...



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