1
Michael W Leddige, Bryce D Horine, Randy Bonella, Peter D MacWilliams: Method and apparatus for implementing multiple memory buses on a memory module. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 1, 2003: US06587912 (302 worldwide citation)

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory ...


2
Michael W Leddige, Bryce D Horine, Randy Bonella, Peter D MacWilliams: Method for implementing multiple memory buses on a memory module. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 5, 2002: US06477614 (236 worldwide citation)

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory ...


3
Michael W Leddige, Bryce D Horine: Method and apparatus for implementing a serial memory architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 7, 2000: US06144576 (122 worldwide citation)

A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive th ...


4
Thomas J Holman, Michael W Leddige: Vertical connector based packaging solution for integrated circuits. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 21, 1999: US06005776 (71 worldwide citation)

An assembly featuring a substrate and a plurality of components. The plurality of components are packaged to be connected in a vertical orientation to the substrate. These components include (i) a vertical chip-scale package (CSP), (ii) an integrated circuit die and (iii) an interconnect. Including ...


5
Bryce D Horine, Michael W Leddige: Method and apparatus for matched length routing of back-to-back package placement. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 5, 2002: US06353539 (26 worldwide citation)

A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad cou ...


6
Michael W Leddige, Bryce D Horine, James A McCall: Multi-layer printed circuit board with signal traces of varying width. Intel Corporation, Mark V Seeley, April 2, 2002: US06366466 (16 worldwide citation)

A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The first signal trace has a relatively thin section and a relatively thick section. The multi-layer printed circuit board also includes a via that couples the f ...


7
Timothy R Block, David P Gaio, Charles J Guenther, Dennis L Karst, Thomas D Kidd, Michael W Leddige: Optical device heat spreader and thermal isolation apparatus. International Business Machines Corporation, Andrew J Dillon, April 30, 1996: US05513073 (15 worldwide citation)

Attachment of electronics to optical devices is made by supporting the optical devices on a heat spreader card and the electronics on a separate circuit card. Each card has at least a first major surface, with an optical transducing subassembly mounted perpendicularly from the major surface of the h ...


8
Pascal C Meier, Michael W Leddige, Mohiuddin Mazumder, Mark Trobough, Alok Tripathi, Ven R Holalkere: Technique for blind-mating daughtercard to mainboard. Intel Corporation, Buckley Maschoff & Talwalkar, July 22, 2008: US07402048 (10 worldwide citation)

An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable (“flex cable”) secured to the PCB. The apparatus also includes a daughter card having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector ...


9
Stephen H Hall, Michael W Leddige: Low weight data encoding for minimal power delivery impact. Intel Corporation, Kenyon & Kenyon, September 7, 2004: US06788222 (10 worldwide citation)

A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data ...


10
Stephen H Hall, Michael W Leddige: System and method for bit encoding to increase data transfer rate. Intel Corporation, Jeffrey B Huter, May 10, 2005: US06891899 (8 worldwide citation)

A system and method for increasing data transfer rate is disclosed. A digital signal waveform that contains one bit of information for every bit time of the digital signal waveform is received. Every three bits of the digital signal waveform is buffered and encoded. The encoding produces an encoded ...