1
Michael R Butts, Jon A Batcheller: Method of using electronically reconfigurable logic circuits. Mentor Graphics Corporation, Klarquist Sparkman Campbell Leigh & Whinston, July 30, 1991: US05036473 (281 worldwide citation)

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable in ...


2
Stephen P Sample, Mikhail Bershteyn, Michael R Butts, Jerry R Bauer: Memory circuit for use in hardware emulation system. Quickturn Design Systems, Orrick Herrington & Sutcliffe, May 4, 2004: US06732068 (186 worldwide citation)

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality o ...


3

4
Michael R Butts, Jon A Batcheller: Hierarchically connected reconfigurable logic assembly. Quickturn Design Systems, Lyon & Lyon, September 19, 1995: US05452231 (141 worldwide citation)

A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigura ...


5
Michael R Butts, Jon A Batcheller: Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system. Quickturn Design Systems, Lyon & Lyon, September 5, 1995: US05448496 (117 worldwide citation)

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable in ...


6
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel: I/O buffer circuit with pin multiplexing. Altera Corporation, Quickturn Design Systems, Lyon & Lyon, February 1, 2000: US06020760 (105 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a ...


7
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel: I/O buffer circuit with pin multiplexing. Altera Corporation, Quickturn Design Systems, Townsend and Townsend and Crew, September 4, 2001: US06285211 (81 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a ...


8
Stephen P Sample, Mikhail Bershteyn, Michael R Butts, Jerry R Bauer: Emulation system with time-multiplexed interconnect. Quickturn Design Systems, Lyon & Lyon, September 28, 1999: US05960191 (80 worldwide citation)

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality o ...


9
Stephen P Sample, Mikhail Bershteyn, Michael R Butts, Jerry R Bauer: Emulation system with time-multiplexed interconnect. Quickturn Design Systems, Lyon & Lyon, April 23, 2002: US06377912 (79 worldwide citation)

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality o ...


10
Michael R Butts, Jon A Batcheller: Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation. Quickturn Design Systems, Lyon & Lyon, August 26, 1997: US05661662 (56 worldwide citation)

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable in ...