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Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. Internation Business Machines Corporation, Daniel P Morris Esq, Perman & Green, April 18, 2006: US07030481 (256 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


2
Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. International Business Machines Corporation, Daniel P Morris, Perman & Green, November 8, 2005: US06962872 (243 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


3
Michael Patrick Chudzik, Irene McStay, Helmut Horst Tews, Porshia Shane Wrschka: Sacrificial collar method for improved deep trench processing. International Business Machines Corporation, Infineon Technologies, Steven Capella, Daryl K Neff, June 14, 2005: US06905944 (16 worldwide citation)

A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etche ...


4
Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T Settlemyer Jr, Padraic C Shafer, Joseph F Shepard Jr: Method and structure for salicide trench capacitor plate electrode. International Business Machines Corporation, Joseph P Abate, Daryl K Neff, December 16, 2003: US06664161 (13 worldwide citation)

The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form ...


5
Anthony I Chih Chou, Michael Patrick Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul Daniel Kirsch, Byoung Hun Lee, Katsunori Onishi, Heemyoung Park, Kristen Colleen Scheer, Akihisa Sekiguchi: Forming gate oxides having multiple thicknesses. International Business Machines Corporation, Howard M Cohn, Rosa Suazo, January 9, 2007: US07160771 (9 worldwide citation)

Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on ...


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Michael Patrick Chudzik, Jochen Beintner, Ramachandra Divakaruni, Rajarao Jammy: Formation of self-aligned buried strap connector. International Business Machines Corporation, Infineon Technologies, Eric W Petraske, June 17, 2003: US06579759 (9 worldwide citation)

In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the te ...


7
James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan: Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes. International Business Machines Corporation, Schmeiser Olsen & Watts, William D Sabo, September 7, 2010: US07790559 (4 worldwide citation)

A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrod ...


8
James William Adkisson, Michael Patrick Chudzik, Jeffrey Peter Gambino, Hongwen Yan: Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes. International Business Machines Corporation, Schmeiser Olsen & Watts, David A Cain, July 24, 2012: US08227874 (2 worldwide citation)

A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate die ...


9
Michael Patrick Chudzik, Paul Daniel Kirsch: Transistors with gate stacks having metal electrodes. International Business Machines Corporation, Schmeiser Olsen & Watts, Ian D MacKinnon, September 6, 2011: US08012863

A transistor with a gate stack having a metal electrode and a method for forming the same. The method includes providing a structure which includes (a) a substrate, (b) a gate dielectric layer on the substrate, and (c) a gate layer on the gate dielectric layer. The gate layer includes an oxidized la ...


10
Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard, Anna Wanda Topol: High density chip carrier with integrated passive devices. Perman & Green, June 10, 2004: US20040108587-A1

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.