1
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus, Blakely Sokoloff Taylor & Zafman, July 4, 1995: US05430676 (107 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


2
Frederick A Ware, James A Gasbarro, John B Dillon, Michael P Farmwald, Mark A Horowitz, Matthew M Griffin: Method and apparatus for implementing refresh in a synchronous DRAM system. Rambus, Blakely Sokoloff Taylor & Zafman, August 29, 1995: US05446696 (95 worldwide citation)

A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can ...


3
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus, Blakely Sokoloff Taylor & Zafman, April 23, 1996: US05511024 (79 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


4
Frederick A Ware, Michael P Farmwald, Craig Hampel, Karnamadakala Krishnamohan: Cache system and method for prefetching of data. Rambus, Blakely Sokoloff Taylor and Zafman, July 16, 1996: US05537573 (57 worldwide citation)

A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache structure and method for implementing the same takes advantage of the previous execution history of the processor and the locality of refere ...


5
Frederick A Ware, John B Dillon, Richard M Barth, Billy Wayne Garrett Jr, John Girdner Atwood Jr, Michael P Farmwald, Richard DeWitt Crisp: Method and apparatus for writing to memory components. Rambus, Blakely Sokoloff Taylor & Zafman, October 21, 1997: US05680361 (56 worldwide citation)

Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and ...


6
Frederick A Ware, John B Dillon, Richard M Barth, Billy Wayne Garrett Jr, John Girdner Atwood Jr, Michael P Farmwald, Richard DeWitt Crisp: Method and apparatus for writing to memory components. Rambus, Blakely Sokoloff Taylor & Zafman, December 1, 1998: US05844855 (52 worldwide citation)

Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit ...


7
George S Taylor, Michael P Farmwald: Two-level translation look-aside buffer using partial addresses for enhanced speed. Silicon Graphics, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226133 (47 worldwide citation)

A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the i ...


8
Frederick A Ware, John B Dillon, Richard M Barth, Billy Wayne Garrett Jr, John Girdner Atwood Jr, Michael P Farmwald, Richard DeWitt Crisp: Method and apparatus for writing to memory components. Rambus, Blakely Sokoloff Taylor & Zafman, August 17, 1999: US05940340 (24 worldwide citation)

Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit ...


9
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus Incorporated, Blakely Sokoloff Taylor & Zafman, July 18, 1995: US05434817 (23 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


10
Frederick A Ware, John B Dillon, Richard M Barth, Billy Wayne Garrett Jr, John Girdner Atwood Jr, Michael P Farmwald, Richard DeWitt Crisp: Method and apparatus for writing to memory components. Rambus, Blakely Sokoloff Taylor & Zafman, September 21, 1999: US05956284 (16 worldwide citation)

Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit ...