1
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer with overlapping windows-div. Visual Information Technologies, Baker & Botts, September 8, 1992: US05146592 (205 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


2
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing system using separate data processor and address generator. Visual Information Technologies, Baker & Botts, January 15, 1991: US04985848 (200 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


3
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer. Visual Information Technologies, Baker & Botts, July 7, 1992: US05129060 (40 worldwide citation)

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addre ...


4
Stephen A Deschaine, Michael K Corry: Time slot interchange digital switched matrix. DSC Communications Corporation, Jerry W Mills, September 13, 1988: US04771420 (33 worldwide citation)

A time slot interchange matrix is comprised of a plurality of matrix modules (50)-(56) each for receiving data on a plurality of channels and transmitting data on the same number of channels. Each of the modules consists of separate banks of random access memory that are interfaced with an intramatr ...


5
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer. Visual Information Technologies, Baker & Botts, April 28, 1992: US05109348 (30 worldwide citation)

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives ...


6
David M Pfeiffer, David T Stoner, John P Norsworthy, Dwight D Dipert, Jay A Thompson, James A Fontaine, Michael K Corry: High speed image processing computer with error correction and logging. Visual Information Technologies, Baker Mills & Glast, September 4, 1990: US04955024 (23 worldwide citation)

Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives ...


7
John P Norsworthy, David T Stoner, Michael K Corry: Memory controller flexible timing control system and method. Pixel Semiconductor, Baker & Botts, January 4, 1994: US05276856 (17 worldwide citation)

There is disclosed a system and method of controlling the timing in a system having a number of different elements, each requiring individual timing signals. The system utilizes a RAM memory divided into a number of groups or cycle types, each cycle type having a number of addressable words. The ind ...


8
John P Norsworthy, David T Stoner, Michael K Corry, David M Pfeiffer: Image memory controller for controlling multiple memories and method of operation. Pixel Semiconductor, Baker & Botts, August 31, 1993: US05241642 (7 worldwide citation)

There is disclosed a memory controller for controlling addresses to a plurality of different memory types while treating the memory system as a whole so as to create a unified addressing arrangement. The controller is structured to allow for a reprogramming of the split address between the memories ...