1
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, March 7, 2000: US06034882 (952 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. ...


2
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 6, 2001: US06185122 (509 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


3
Michael Farmwald, Mark Horowitz: Apparatus for synchronously generating clock signals in a data processing system. Rambus, Blakely Sokoloff Taylor & Zafman, September 7, 1993: US05243703 (374 worldwide citation)

An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its f ...


4
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Brinks Hoffer Gilson & Lione, November 19, 2002: US06483736 (294 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


5
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 26, 2002: US06351406 (289 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


6
Michael Farmwald, Mark Horowitz: Integrated circuit I/O using high performance bus interface. Rambus, Blakely Sokoloff Taylor & Zafman, June 7, 1994: US05319755 (277 worldwide citation)

An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecti ...


7
Michael Farmwald, Mark Horowitz: Memory circuitry having bus interface for receiving information in packets and access time registers. Rambus, Blakeley Sokoloff Taylor & Zafman, February 25, 1997: US05606717 (258 worldwide citation)

An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a pluralit ...


8
Thomas H Lee, Vivek Subramanian, James M Cleeves, Andrew J Walker, Christopher J Petti, Igor G Kouznetzov, Mark G Johnson, Paul Michael Farmwald, Brad Herner: Monolithic three dimensional array of charge storage devices containing a planarized surface. Matrix Semiconductor, Foley & Lardner, April 19, 2005: US06881994 (256 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


9
Michael Farmwald, Mark Horowitz: Memory module having memory devices containing internal device ID registers and method of initializing same. Rambus, Steinberg & Whitt, July 27, 1999: US05928343 (250 worldwide citation)

A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a ...


10
Michael Farmwald, Mark Horowitz: Integrated circuit I/O using a high performance bus interface. Rambus, Blakely Sokoloff Taylor & Zafman, April 30, 1996: US05513327 (166 worldwide citation)

A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting ea ...