1
Christopher N Brindle, Michael A Stuber, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener: Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink. Peregrine Semiconductor Corporation, Jaquez & Associates, Martin J Jaquez Esq, March 22, 2011: US07910993 (121 worldwide citation)

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET perfo ...


2
Michael A Stuber, Christopher N Brindle, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener, Alexander Dribinsky, Tae Youn Kim: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Jaquez & Associates, Martin J Jaquez Esq, Larry D Flesner, February 15, 2011: US07890891 (55 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


3
Christopher N Brindle, Michael A Stuber, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener: Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink. Peregrine Semiconductor Corporation, Jaquez & Associates, Martin J Jaquez Esq, March 6, 2012: US08129787 (50 worldwide citation)

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET perfo ...


4
Chris Brindle, Michael A Stuber, Stuart B Molin: Trap rich layer for semiconductor devices. IO Semiconductor, The Mueller Law Office P C, June 18, 2013: US08466036 (35 worldwide citation)

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, an ...


5
James S Cable, Eugene F Lyons, Michael A Stuber, Mark L Burgener: Radiation-hardened silicon-on-insulator CMOS device, and method of making the same. Peregrine Semiconductor Corporation, Morrison & Foerster, March 11, 2003: US06531739 (33 worldwide citation)

A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the inte ...


6
Christopher N Brindle, Michael A Stuber, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Robert B Welstand, Mark L Burgener: Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink. Peregrine Semiconductor Corporation, Jaquez & Associates, Martin J Jaquez Esq, March 26, 2013: US08405147 (21 worldwide citation)

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET perfo ...


7
Anton Arriagada, Chris Brindle, Michael A Stuber: Trap rich layer with through-silicon-vias in semiconductor devices. IO Semiconductor, The Mueller Law Office P C, July 9, 2013: US08481405 (14 worldwide citation)

An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, a ...


8
Christopher N Brindle, Michael A Stuber, Dylan J Kelly, Clint L Kemerling, George Imthurn, Robert B Welstand, Mark L Burgener: Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink. Peregrine Semiconductor Corporation, Jaquez Land Richman, Mark J Jaquez Esq, September 8, 2015: US09130564 (11 worldwide citation)

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET perfo ...


9
Michael A Stuber, Christopher N Brindle, Dylan J Kelly, Clint L Kemerling, George P Imthurn, Mark L Burgener, Alexander Dribinsky, Tae Youn Kim: Method and apparatus improving gate oxide reliability by controlling accumulated charge. Peregrine Semiconductor Corporation, Jaquez Land Richman, Martin J Jaquez Esq, February 10, 2015: US08954902 (11 worldwide citation)

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwis ...


10
Anton Arriagada, Michael A Stuber, Stuart B Molin: Trap rich layer formation techniques for semiconductor devices. IO Semiconductor, The Mueller Law Office P C, September 17, 2013: US08536021 (10 worldwide citation)

A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation ...