1
Michael A Kozuch, James A Sutton II, David Grawrock, Gilbert Neiger, Richard A Uhlig, Bradley G Burgess, David I Poisner, Clifford D Hall, Andy Glew, Lawrence O Smith III, Robert George: Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 2006: US07024555 (30 worldwide citation)

An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection el ...


2
Steve Bennett, Andrew V Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Michael A Kozuch: Control over faults occurring during the operation of guest software in the virtual-machine architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 17, 2006: US07124327 (21 worldwide citation)

In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more filtering criterion. If the determination is positive, control remains with the guest softw ...


3
Hong Wang, Ralph Kling, Yong Fong Lee, David A Berson, Michael A Kozuch, Konrad Lai: Processing essential and non-essential code separately. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, March 28, 2006: US07020766 (18 worldwide citation)

A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion ...


4
Erik C Cota Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A Kozuch, Gilbert Neiger, Richard Uhlig: Invalidating translation lookaside buffer entries in a virtual machine (VM) system. Intel Corporation, David P McAbee, January 4, 2011: US07865670 (14 worldwide citation)

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidate ...


5
Steve Bennett, Andrew V Anderson, Erik Cota Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Michael A Kozuch: Control register access virtualization performance improvement in the virtual-machine architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 24, 2006: US07127548 (12 worldwide citation)

In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the ...


6
Andy Glew, Michael A Kozuch, Erich S Boleyn, Lawrence O Smith III, Gilbert Neiger, Richard Uhlig: Method and apparatus for translating guest physical addresses in a virtual machine environment. Intel Corporation, Thomas R Lane, October 17, 2006: US07124273 (11 worldwide citation)

A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.


7
Steven M Bennett, Gilbert Neiger, Erik C Cota Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A Kozuch, Richard A Uhlig: Methods and systems to manage machine state in virtual machine operations. Intel Corporation, Thomas R Lane, September 7, 2010: US07793286 (6 worldwide citation)

Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in ...


8
Michael A Kozuch, James A Sutton, David Grawrock: Method and apparatus for loading a trustable operating system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 8, 2009: US07631196 (5 worldwide citation)

A method and apparatus is provided in which a trustable operating system is loaded into a region in memory. A start secure operation (SSO) triggers a join secure operation (JSO) to halt all but one central processing unit (CPU) in a multi-processor computer. The SSO causes the active CPU to load a c ...


9
Eric C Cota Robles, Andy Glew, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A Kozuch, Gilbert Neiger, Richard Uhlig: Invalidating translation lookaside buffer entries in a virtual machine (VM) system. Intel Corporation, Thomas R Lane, September 24, 2013: US08543772 (5 worldwide citation)

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidate ...


10
Andrew F Glew, James A Sutton, Lawrence O Smith, David W Grawrock, Gilbert Neiger, Michael A Kozuch: Authenticated code module. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 11, 2007: US07308576 (4 worldwide citation)

An authenticated code module comprises a value that attests to the authenticity of the module. The value is encrypted with a key corresponding to a key of a computing device that is to execute the module.