1
Glenn J Hinton, David B Papworth, Andrew F Glew, Michael A Fetterman, Robert P Colwell: Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 24, 1998: US05721855 (179 worldwide citation)

A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an in ...


2
Bradley D Hoyt, Glenn J Hinton, David B Papworth, Ashwani K Gupta, Michael A Fetterman, Subramanian Natarajan, Sunil Shenoy, Reynold V D Sa: Method and apparatus for resolving return from subroutine instructions in a computer processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 18, 1997: US05604877 (91 worldwide citation)

A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the ...


3
David B Papworth, Michael A Fetterman, Andrew F Glew, Lawrence O Smith III, Michael M Hancock, Beth Schultz: Apparatus and method for handling string operations in a pipelined processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 1995: US05404473 (78 worldwide citation)

In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a ...


4
Scott Dion Rodgers, Rohit Vidwans, Joel Huang, Michael A Fetterman, Kamla Huck: Method and apparatus for generating event handler vectors based on both operating mode and event type. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1999: US05889982 (77 worldwide citation)

A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is gene ...


5
Bradley D Hoyt, Glenn J Hinton, David B Papworth, Ashwani K Gupta, Michael A Fetterman, Subramanian Natarajan, Sunil Shenoy, Reynold V D Sa: Method and apparatus for implementing a set-associative branch target buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 12, 1996: US05574871 (69 worldwide citation)

A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch in ...


6
Glenn J Hinton, Robert W Martell, Michael A Fetterman, David B Papworth, James L Schwartz: Circuit and method for scheduling instructions by predicting future availability of resources required for execution. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 10, 1996: US05555432 (67 worldwide citation)

An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instructi ...


7
David B Papworth, Andrew F Glew, Glenn J Hinton, Robert P Colwell, Michael A Fetterman, Shantanu R Gupta, James S Griffith: Method and apparatus for dynamic allocation of multiple buffers in a processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 7, 1998: US05778245 (60 worldwide citation)

A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-or ...


8
Robert P Colwell, Andrew F Glew, Atiq A Bajwa, Glenn J Hinton, Michael A Fetterman: Flag renaming and flag masks within register alias table. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 2000: US06047369 (51 worldwide citation)

A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, ...


9
David B Papworth, Andrew F Glew, Michael A Fetterman, Glenn J Hinton, Robert P Colwell, Steven J Griffith, Shantanu R Gupta, Narayan Hegde: Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 10, 1996: US05584038 (47 worldwide citation)

An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an ...


10
David B Papworth, Michael A Fetterman, Andrew F Glew, Robert P Colwell, Glenn J Hinton: Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 20, 2000: US06079014 (45 worldwide citation)

A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming circuit that allocates execution resources to each instruction, and an execution circuit that executes each ...