1
Michael A Callander: Write-back cache with ECC protection. Digital Equipment Corporation, William P Skladony, Ronald E Myrick, Barry N Young, August 3, 1993: US05233616 (60 worldwide citation)

This invention relates to a write-back cache which is protected with parity and error correction coding ("ECC"). The parity and ECC codes are generated by a memory interface when data is transferred by main memory to the central processing unit ("CPU") associated with the cache. Thus, all data origi ...


2
Douglas E Sanders, Michael A Callander: Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol. Digital Equipment Corporation, Denis G Maloney, Barry Young, Ronald Myrick, March 9, 1993: US05193163 (47 worldwide citation)

A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately av ...


3
Michael A Callander, Douglas E Sanders: Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions. Digital Equipment Corporation, Albert P Cefalo, A Sidney Johnston, James F Thompson, January 4, 1994: US05276852 (35 worldwide citation)

A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants con ...


4
Michael A Callander, G Michael Uhler, W Hugh Durdan: Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions. Digital Equipment Corporation, Mark J Casey, Denis G Maloney, Arthur W Fisher, November 26, 1996: US05579504 (32 worldwide citation)

Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many ...


5
Michael A Callander, Linda Chao, Douglas E Sanders: Apparatus for suppressing an error report from an address for which an error has already been reported. Digital Equipment Corporation, Barry N Young, Ronald C Hudgens, July 6, 1993: US05226150 (28 worldwide citation)

A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also ...