1
Mel Bazes: CMOS digital clock and data recovery circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 7, 1992: US05103466 (62 worldwide citation)

An integrated circuit for recovering the clock and data information from phase-encoded serial data. The circuit includes a synchronous delay line coupled to a waveform digitizer and a waveform synthesizer. The waveform digitizer receives and converts the phase-encoded data into a string of bits whos ...


2
Mel Bazes, Rafi Ben Tal: Adaptive equalization using a minimum- jitter criterion. Intel Corporation, Kenyon & Kenyon, November 23, 1999: US05991339 (51 worldwide citation)

An adaptive equalizer is implemented using digital feedback control and using jitter as the adjustment criteria. An adjustable transfer function is implemented to equalize an input signal to enhance the frequency response of the associated system. Jitter is determined for the filtered signal, and th ...


3
Mel Bazes: Method and apparatus for detecting differential threshold levels while compensating for baseline wander. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 9, 1999: US05880615 (43 worldwide citation)

A method and an apparatus for detecting differential threshold levels of a differential signal being carried in first and second lines while compensating for baseline wander. In one embodiment, first and second single-ended signals and a common mode signal are generated in response to the first and ...


4
Mel Bazes: CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 18, 1990: US04958133 (43 worldwide citation)

A CMOS complementary, self-biased, differential amplifier provides for a rail-to-rail common-mode input-voltage range of operation. A self-biasing scheme is used to provide negative feedback to the amplifier in order to assist in providing a common-mode rejection but providing high gain amplificatio ...


5
Mel Bazes: Self-biased, high-gain differential amplifier with feedback. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 26, 1990: US04937476 (40 worldwide citation)

A self-biased, high-gain differential amplifier which is substantially immune to process and temperature variations. A first pair of CMOS transistors is coupled to operate in an active region and an output from the common junction is coupled to drive a second pair of CMOS transistors. The second pai ...


6
Mel Bazes: Method and apparatus for reducing baseline wander. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 31, 2000: US06140857 (38 worldwide citation)

A method and an apparatus for reducing baseline wander in a differential signal. In one embodiment, the differential signal is carried in first and second signal lines. If negative baseline wander is detected in the differential signal, a first pair of current sources is activated. One of the first ...


7
Mel Bazes: CMOS clock-phase synthesizer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 30, 1991: US05036230 (37 worldwide citation)

An integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed. The sequence control apparatus is coupled to a waveform synthesizer apparatus producing at least one clock-phase output. The clock-phase output from the wav ...


8
Mel Bazes: Integrated circuit synchronous delay line. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 29, 1985: US04496861 (37 worldwide citation)

A synchronized delay line is described which is tapped to provide a plurality of timing signals. The delay line is insensitive to voltage changes, temperature changes and wafer processing variations. It is ideally suited for providing on-chip timing signals derived from a reference clock for MOS int ...


9
Mel Bazes: CMOS input buffer with switched capacitor reference voltage generator. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 18, 1989: US04849661 (32 worldwide citation)

An input buffer circuit for providing corresponding CMOS compatible signals to an input signal. The input buffer circuit is comprised of a switched-capacitor voltage division network for providing a reference voltage to a comparator. The comparator accepts an input voltage and determines if the inpu ...


10
Mel Bazes: Binomially-encoded finite state machine. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 23, 1987: US04675556 (24 worldwide citation)

A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The state signals are used to activate the AND plane ...