1
Victor Chan, Kathryn W Guarini, Meikei Ieong: Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers. International Business Machines Corporation, Wan Yee Cheung Esq, Scully Scott Murphy & Presser, November 23, 2004: US06821826 (141 worldwide citation)

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D ...


2
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Rafael Perez Piniero Esq, December 25, 2007: US07312487 (117 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


3
Diane C Boyd, Judson R Holt, MeiKei Ieong, Renee T Mo, Zhibin Ren, Ghavam G Shahidi: Ultra-thin body super-steep retrograde well (SSRW) FET devices. International Business Machines Corporation, Graham S Jones II, H Daniel Schnurmann, February 21, 2006: US07002214 (108 worldwide citation)

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. ...


4
Anda C Mocuta, Meikei Ieong, Ricky S Amos, Diane C Boyd, Dan M Mocuta, Huajie Chen: High performance CMOS device structure with mid-gap metal gate. International Business Machines Corporation, Scully Scott Murphy & Presser, Joseph P Abate Esq, July 12, 2005: US06916698 (106 worldwide citation)

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The pre ...


5
Andres Bryant, Meikei Ieong, K Paul Muller, Edward J Nowak, David M Fried, Jed Rankin: Double gated transistor and method of fabrication. International Business Machines Corporation, Schmeiser Olsen & Watts, Richard M Kotulak, October 30, 2007: US07288445 (104 worldwide citation)

Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the dou ...


6
Meikei Ieong, Omer H Dokumaci, Thomas S Kanarsky, Victor Ku: Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate, May 9, 2006: US07041538 (96 worldwide citation)

A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining ...


7
Jack Oon Chu, Bruce B Doris, Meikei Ieong, Jing Wang: Metal gated ultra short MOSFET devices. International Business Machines Corporation, George Sai Halasz, Robert M Trepp, March 25, 2008: US07348629 (93 worldwide citation)

MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body lay ...


8
Jack Oon Chu, Bruce B Doris, Meikei Ieong, Jing Wang: Metal gated ultra short MOSFET devices. International Business Machines Corporation, George Sai Halasz, March 16, 2010: US07678638 (92 worldwide citation)

MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body lay ...


9
Jack Oon Chu, Bruce B Doris, Meikei Ieong, Jing Wang: Method for metal gated ultra short MOSFET devices. International Business Machines Corporation, George Sai Halasz, Robert M Trepp, February 24, 2009: US07494861 (92 worldwide citation)

MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body lay ...


10
MeiKei Ieong, Edward J Nowak: Variable threshold voltage double gated transistors and method of fabrication. International Business Machines Corporation, Schmeiser Olsen & Watts, December 10, 2002: US06492212 (89 worldwide citation)

The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having different body widths. By forming double gate transi ...



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