1
Ricky C Hetherington, Tryggve Fossum, Maurice B Steinman, David A Webb Jr: Write back buffer with error correcting capabilities. Digital Equipment Corporation, Arnold White & Durkee, February 19, 1991: US04995041 (47 worldwide citation)

In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expecte ...


2
Maurice B Steinman, Richard E Kessler, Gregg A Bouchard: Computer architecture and system for efficient management of bi-directional bus. Hewlett Packard Development Company, March 9, 2004: US06704817 (40 worldwide citation)

An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ...


3
David W Hartwell, Maurice B Steinman: Restoring access to a failed data storage device in a redundant memory system. Hewlett Packard Development Company, April 3, 2007: US07200770 (35 worldwide citation)

A computer system comprising a memory system that comprises a plurality of memory modules; and a memory controller that accesses the plurality of memory modules to service memory requests. The computer system also comprises an error-type memory controller that configures the noted access such that t ...


4
Richard E Kessler, Michael S Bertone, Michael C Braganza, Gregg A Bouchard, Maurice B Steinman: System for minimizing memory bank conflicts in a computer system. Hewlett Packard Development Company, September 16, 2003: US06622225 (31 worldwide citation)

A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to different m ...


5
Richard E Kessler, Michael S Bertone, Gregg A Bouchard, Maurice B Steinman: Computer resource management and allocation system. Hewlett Packard Development Company, June 22, 2004: US06754739 (28 worldwide citation)

A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or ...


6
Maurice B Steinman, Gregg A Bouchard: Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth. Hewlett Packard Development Company, July 8, 2003: US06591349 (28 worldwide citation)

A system and method is disclosed to increase computer memory system performance by reducing lost clock cycles caused by bus turnarounds. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows w ...


7
Denis Foley, Maurice B Steinman, Stephen R VanDoren: Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system. Digital Equipment Corporation, Mark J Casey, Denis G Maloney, Arthur W Fisher, September 24, 1996: US05559987 (19 worldwide citation)

A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modific ...


8
Alexander Branover, Maurice B Steinman, Anthony Asaro, James B Fry: Method and apparatus for memory power management. Advanced Micro Devices, ATI Technologies ULC, Meyertons Hood Kivlin Kowert & Goetzel, Erik A Heter, February 18, 2014: US08656198 (11 worldwide citation)

A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if a ...


9
Richard E Kessler, Maurice B Steinman, Peter J Bannon, Michael C Braganza, Gregg A Bouchard: Proprammable DRAM address mapping mechanism. Compaq Information Technologies Group, Michael F Beim, Jonathan M Harris, Conley Rose P C, April 8, 2003: US06546453 (10 worldwide citation)

A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cac ...


10
Richard E Kessler, Peter J Bannon, Maurice B Steinman, Scott E Breach, Allen J Baum, Gregg A Bouchard: Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature. Hewlett Packard Development Company, October 21, 2003: US06636955 (10 worldwide citation)

A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller prefe ...