1
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Method and apparatus for sharing access to a bus. Intel Corporation, Fish & Richardson P C, October 8, 2002: US06463072 (70 worldwide citation)

A router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at ...


2
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Scratchpad memory. Intel Corporation, Fish & Richardson P C, December 23, 2003: US06667920 (69 worldwide citation)

An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.


3
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Scratchpad memory. Intel Corporation, Fish & Richardson P C, October 23, 2001: US06307789 (66 worldwide citation)

An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.


4
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Scratchpad memory. Intel Corporation, Fish & Richardson P C, June 10, 2003: US06577542 (60 worldwide citation)

An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.


5
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Scratchpad memory. Intel Corporation, Fish & Richardson P C, April 5, 2005: US06876561 (28 worldwide citation)

An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.


6
Michael Ho, Miriam Qunell, Jason Garratt, Kevin Citterelle, Jeff Fedders, Michael Kauschke, Matthew Adiletta, Ernest Kaempfer, Douglas Carrigan: Techniques for transmitting and receiving traffic over advanced switching compatible switch fabrics. Blakely Sokoloff Taylor & Zafman, September 1, 2009: US07583664 (18 worldwide citation)

Techniques for transmitting SONET/SDH traffic over an Advanced Switching compatible switch fabric. In one implementation, SONET/SDH traffic may be aggregated and encapsulated into Advanced Switching compatible packets. In one implementation, the contents of the Advanced Switching compatible packets ...


7
Gilbert Wolrich, Matthew Adiletta, William R Wheeler: Processor having a dedicated hash unit integrated within. Intel Corporation, June 22, 2010: US07743235 (14 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a firs ...


8
Matthew Adiletta, Robert Stepanian, Teresa Meng: Method and apparatus for configuring compressed data coefficients to minimize transpose operations. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, October 16, 2001: US06304604 (8 worldwide citation)

A method for decompressing compressed data elements, drawing that decompression operation, the intermediate coefficients are organized in a matrix configuration such that the number of transpose operations are minimized. The organization of that matrix includes storing sequential coefficients, trans ...


9
Matthew Adiletta: Method and apparatus for viedo compression and decompression using high speed discrete cosine transform. Digital Equipment Coporation, Ronald C Hudgens, Arthur W Fisher, August 11, 1998: US05793658 (8 worldwide citation)

A method and apparatus performs high speed forward or reverse Discrete Cosine Transform (DCT) for video compression and decompression that is optimized in both directions and which uses minimal hardware. This invention can be used to improve the speed of electronic transmission of images, decrease t ...


10
Jeffrey G Fedders, Matthew Adiletta, Valerie J Young: Distributing intelligence across networks. Intel Corporation, Caven & Aghevli, August 14, 2012: US08243596 (7 worldwide citation)

Methods and apparatus relating to distribution of intelligence across a network are described. In one embodiment, one or more content processors may be provided at the edge of a computer network (e.g., prior to a point where data is aggregated or routed by the network). Other embodiments are also di ...