1
Qiushi Chen, Beifang Qiu, Charles C Chiang, Xiaoping Hu, Mathew Koshy, Baribrata Biswas: Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs. Synopsys, Park Vaughan Fleming & Dowler, March 27, 2012: US08146032 (19 worldwide citation)

One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, ...


2
David White, Roland Ruehl, Mathew Koshy: System and method for performing verification based upon both rules and models. Cadence Design Systems, Vista IP Law Group, April 27, 2010: US07707528 (13 worldwide citation)

Methods and systems for integrating both models and rules into a verification flow to address both of these issues. Models are employed to perform simulations to provide more accurate verification results. In addition, the lithography simulation results can be used to fine-tune the rules themselves ...


3
David White, Roland Ruehl, Mathew Koshy: System and method for model-based scoring and yield prediction. Cadence Design Systems, Vista IP Law Group, March 30, 2010: US07689948 (11 worldwide citation)

Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured ...


4
Udayan Gumaste, Roland Ruehl, Mathew Koshy, Harsh Deshmane: System and method for using rules-based analysis to enhance models-based analysis. Cadence Design Systems, Vista IP Law Group, February 8, 2011: US07886243 (5 worldwide citation)

The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify s ...


5
Mathew Koshy, Roland Ruehl, Min Cao, Li Ling Ma, Eitan Cadouri, Tianhao Zhang: Method and system for parallel processing of IC design layouts. Cadence Design Systems, Vista IP Law Group, February 2, 2010: US07657856 (3 worldwide citation)

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are pe ...


6
Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas: Capacitance extraction for advanced device technologies. Synopsys, Blakely Sokoloff Taylor & Zafman, Judith A Szepesi, August 27, 2013: US08522181 (3 worldwide citation)

A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a devi ...


7
Xiaojun Wang, Roland Ruehl, Li Ling Ma, Mathew Koshy, Tianhao Zhang, Udayan Gumaste, Krzysztof Antoni Kozminski, Haifang Liao, Xinming Tu, Xu Zhu: Method and system for parallel processing of IC design layouts. Cadence Design Systems, Vista IP Law Group, May 21, 2013: US08448096 (1 worldwide citation)

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are pe ...


8
Arthur Nieuwoudt, Jiyoun Kim, Mathew Koshy, Baribrata Biswas: Capacitance extraction for advanced device technologies. Synopsys, HIPLegal, Judith A Szepesi, October 14, 2014: US08863055

A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical ...


9
Roland Ruehl, Mathew Koshy, Jonathan Fales, Udayan Gumaste: System and method for random defect yield simulation of chip with built-in redundancy. Cadence Design Systems, Vista IP Law Group, July 19, 2011: US07984399

In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips w ...


10
Mada Kannan Arunachala Nadar, Thampan Tony Mathew Koshy: Novel membrane electrode assemblies. Hoku Scient, March 7, 2007: EP1759431-A2

A process for producing a catalyzed membrane is described. The process includes mixing components of a catalyst to produce a catalyst mixture, wherein one of the component includes an aprotic solvent and applying the catalyst mixture to a membrane to produce the catalyzed membrane.