1
Tetsuji Tsutsumi, Toshiyuki Nishii, Masayuki Takeshige: Method of replacing failed memory cells in semiconductor memory device. Fujitsu, Arent Fox Kintner Plotkin & Kahn, September 5, 2000: US06115828 (40 worldwide citation)

A memory having a plurality of memory cells and a plurality of redundant memory cells accesses a redundant memory cell in lieu of a failed memory cell. The memory is tested for failed memory cells. Addresses of detected failed memory cells are stored in a first set of registers, and addresses of red ...


2
Masayuki Takeshige, Sumitaka Hibino, Kenji Yamada: Test method and test system for semiconductor device. Fujitsu, Arent Fox PLLC, March 14, 2006: US07013414 (5 worldwide citation)

Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator rec ...


3
Masayuki Takeshige: Method and apparatus for determining the number of words of transferred data in a digital data transfer system. Fujitsu, Fujitsu VLSI, Staas & Halsey, December 3, 1996: US05581711 (2 worldwide citation)

An apparatus and method for transferring digital data is herein disclosed using a central processing unit and a direct memory access controller. Based on the control of the central processing unit, a direct memory access controller counts the number of words stored in a memory device by determining ...


4
Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi: Method and apparatus for compactly storing instruction codes. Fujitsu, Staas & Halsey, December 31, 2002: US06502179 (1 worldwide citation)

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores ...


5
Teruyoshi Kondo, Masayuki Takeshige, Sumitaka Hibino, Hayato Isobe, Yukisato Miyazaki, Kunihiro Ohara, Kazuya Taniguchi, Hiroshi Naritomi: Processor and information processing method. Staas & Halsey, February 21, 2002: US20020023205-A1

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores ...


6
Masayuki Takeshige, Sumitaka Hibino, Kenji Yamada: Test method and test system for semiconductor device. Fujitsu, Arent Fox Kintner Plotkin & Kahn Pllc, December 12, 2002: US20020188900-A1

Method and system for shorten time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives p ...